CY7C1049CV33-20VC Cypress Semiconductor Corp, CY7C1049CV33-20VC Datasheet - Page 3

• Manufacturer Part Number: CY7C1049CV33-20VC
• Description: IC SRAM 4MBIT 20NS 36SOJ
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1049CV33-20VC

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (512K x 8)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 36-SOJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1488-5

Document #: 38-05006 Rev. *B
AC Switching Characteristics
Switching Waveforms
Read Cycle No. 1
Notes:
10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
12. Device is continuously selected. OE, CE = V
13. WE is HIGH for Read cycle.
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
6.
7.
8.
9.
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
Parameter
DATA OUT
ADDRESS
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
t
t
At any given temperature and voltage condition, t
these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
POWER
HZOE
[7]
, t
HZCE
gives the minimum amount of time that the power supply should be at stable, typical V
[10, 11]
, and t
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
WE LOW to High-Z
CC
HZWE
[12, 13]
(typical) to the first access
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
PREVIOUS DATA VALID
Description
[9]
[8, 9]
[9]
[8, 9]
[8, 9]
IL
[6]
.
t
Over the Operating Range
OHA
HZCE
is less than t
t
AA
LZCE
Min.
1
8
3
0
3
0
8
6
6
0
0
6
4
0
3
, t
HZOE
-8
[2]
Max.
is less than t
8
8
4
4
4
8
4
t
RC
Min.
LZOE
10
10
1
3
0
3
0
7
7
0
0
7
5
0
3
, and t
-10
HZWE
CC
Max.
values until the first memory access can be performed.
HZWE
10
10
10
and t
5
5
5
5
is less than t
SD
.
Min.
12
12
1
3
0
3
0
8
8
0
0
8
6
0
3
-12
LZWE
DATA VALID
Max.
12
12
12
6
6
6
6
for any given device.
CY7C1049CV33
Min.
15
15
10
10
10
1
0
3
0
0
0
7
0
3
-15
Max.
15
15
15
3
7
7
7
7
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Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s