CY7C1049CV33-20VXC Cypress Semiconductor Corp, CY7C1049CV33-20VXC Datasheet - Page 5

• Manufacturer Part Number: CY7C1049CV33-20VXC
• Description: IC SRAM 4MBIT 20NS 36SOJ
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1049CV33-20VXC

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (512K x 8)
• Speed: 20ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 36-SOJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1738; CY7C1049CV3320VXC; CY7C1049CV3320VXC

Document #: 38-05006 Rev. *E
AC Switching Characteristics
AC Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Shaded areas contain advance information.
Read Cycle
t
t
t
t
t
t
Notes:
10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
power
RC
AA
OHA
ACE
DOE
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. t
8. t
9. At any given temperature and voltage condition, t
Parameter
Parameter
of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
POWER
HZOE
[7]
[7]
, t
HZCE
gives the minimum amount of time that the power supply should be at stable, typical V
, and t
[10, 11]
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
WE LOW to High-Z
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
CC
CC
HZWE
(typical) to the first access
(typical) to the first access
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
Description
[9]
[8, 9]
[8, 9]
[9]
[8, 9]
Description
Over the Operating Range
Over the Operating Range
HZCE
is less than t
LZCE
Min.
, t
1
8
3
0
3
0
8
6
6
0
0
6
4
0
3
HZOE
is less than t
-8
[6]
[6]
Max.
8
8
4
4
4
8
4
LZOE
Min.
15
1
, and t
HZWE
CC
Min.
-15
10
10
values until the first memory access can be performed.
1
3
0
3
0
7
7
0
0
7
5
0
3
HZWE
and t
-10
Max.
is less than t
SD
15
15
3
7
.
Max.
10
10
10
5
5
5
5
LZWE
Min.
for any given device.
20
Min.
1
12
12
1
3
0
3
0
8
8
0
0
8
6
0
3
CY7C1049CV33
-20
-12
Max.
Max.
12
12
12
20
20
6
6
6
6
3
8
Page 5 of 11
Unit
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
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