CY7C1049-15VC Cypress Semiconductor Corporation., CY7C1049-15VC Datasheet

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CY7C1049-15VC

Manufacturer Part Number
CY7C1049-15VC
Description
15ns, 512Kx8 static RAM (SRAM)
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
049
Features
Functional Description
The CY7C1049 is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Selection Guide
Cypress Semiconductor Corporation
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Shaded areas contain advance information.
• High speed
• Low active power
• Low CMOS standby power (Commercial L version)
• 2.0V Data Retention (400 W at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
WE
CE
OE
Logic Block Diagram
— t
— 1210 mW (max.)
— 2.75 mW (max.)
A
A
A
A
A
A
A
A
A
A
A
10
0
1
2
3
4
5
6
7
8
9
AA
= 15 ns
INPUT BUFFER
DECODER
COLUMN
512K x 8
ARRAY
Com’l
Com’l
Ind’l
Military
POWER
DOWN
L
3901 North First Street
PRELIMINARY
7C1049-12
240
0.5
12
8
9
1049–1
is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. Writing to the de-
vice is accomplished by taking chip enable (CE) and write en-
able (WE) inputs LOW. Data on the eight I/O pins (I/O
I/O
pins (A
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write en-
able (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049 is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7C1049-15
7
0
1
2
3
4
5
6
7
) is then written into the location specified on the address
220
0.5
15
8
9
0
through A
San Jose
7C1049-17
18
512K x 8 Static RAM
195
).
0.5
17
December 1996 – Revised April 6, 1998
Pin Configuration
8
9
GND
I/O3
I/O
I/O
V
I/O
WE
CE
CC
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
0
1
2
5
6
7
8
9
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CA 95134
0
SOJ
7C1049-20
through I/O
185
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
0.5
20
10
8
9
NC
A
A
A
A
OE
I/O
I/O
GND
V
I/O
I/O
A
A
A
A
A
NC
18
17
16
15
CC
14
13
12
11
10
CY7C1049
7
6
5
4
1049–2
7
) are placed in a
408-943-2600
7C1049-25
180
0.5
25
10
0
8
9
through

Related parts for CY7C1049-15VC

CY7C1049-15VC Summary of contents

Page 1

... Data Retention (400 W at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features Functional Description The CY7C1049 is a high-performance CMOS static RAM or- ganized as 524,288 words by 8 bits. Easy memory expansion Logic Block Diagram INPUT BUFFER A ...

Page 2

... CE > > < MAX , Com’l CC – 0.3V, CC Com’l L > V – 0.3V < 0.3V, f=0 Ind’l IN Military 2 CY7C1049 Ambient [2] Temperature +70 C 4.5V–5.5V – +85 C – +125 C 7C1049-15 7C1049-17 Max. Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0.4 V 2 ...

Page 3

... IN IL MAX Max Com’ > V – 0.3V, CC Com’ > V – 0.3V Ind’ < 0.3V, f=0 IN Military Test Conditions MHz 5. CY7C1049 7C1049-20 7C1049-25 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 2 0.3 0.3 –0.3 0.8 –0.3 0.8 –1 +1 –1 +1 –1 +1 –1 ...

Page 4

... PRELIMINARY 4 CY7C1049 ...

Page 5

... HZCE LZCE HZOE LZOE HZWE 5 CY7C1049 ALL INPUT PULSES 90% 90% 10% 3ns 7C1049-15 7C1049-17 Min. Max. Min. Max ...

Page 6

... Over the Operating Range Conditions Com’ > Ind’l V > Military 6 CY7C1049 7C1049-20 7C1049-25 Max. Min. Max ...

Page 7

... WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. PRELIMINARY DATA RETENTION MODE 3.0V V > CDR OHA DOE DATA VALID 50 CY7C1049 3. 1049–5 DATA VALID 1049–6 t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB 1049–7 ...

Page 8

... During this period the I/Os are in the output state and input signals should not be applied. PRELIMINARY SCE SCE PWE t SD DATA VALID [14, 15 SCE PWE t SD DATA VALID IN 8 CY7C1049 1049– 1049–9 ...

Page 9

... Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS NOTE 16 DATA I/O t HZWE Ordering Information Speed (ns) Ordering Code 15 CY7C1049-15VC CY7C1049L-15VC 17 CY7C1049-17VC CY7C1049L-17VC 20 CY7C1049-20VC CY7C1049L-20VC CY7C1049-20VI CY7C1049L-20VI CY7C1049-20VM CY7C1049L-20VM 25 CY7C1049-25VC CY7C1049L-25VC CY7C1049-25VI CY7C1049L-25VI CY7C1049-25VM CY7C1049L-25VM Shaded areas contain advance information. Document #: 38–00563–B © ...

Page 10

... Package Diagram PRELIMINARY 36-Lead (400-Mil) Molded SOJ V36 10 CY7C1049 ...

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