CY7C182-25PC Cypress Semiconductor Corporation., CY7C182-25PC Datasheet

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CY7C182-25PC

Manufacturer Part Number
CY7C182-25PC
Description
8Kx9 Static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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182
Cypress Semiconductor Corporation
Document #: 38-05031 Rev. **
Features
Functional Description
The CY7C182 is a high-speed CMOS static RAM organized
as 8,192 by 9 bits and it is manufactured using Cypress’s high-
performance CMOS technology. Access times as fast as 25 ns
are available with maximum power consumption of only 770
mW.
Selection Guide
Logic Block Diagram
• High speed
• x9 organization is ideal for cache memory applications
• CMOS for optimum speed/power
• Low active power
• Low standby power
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Easy memory expansion with CE
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
— t
— 770 mW
— 195 mW
AA
CE
CE
WE
OE
= 25 ns
1
2
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
INPUT BUFFER
DECODER
256 x 32 x 9
COLUMN
ARRAY
1
, CE
2
, OE options
3901 North First Street
POWER
DOWN
7C182-25
140
25
35
The CY7C182, which is oriented toward cache memory appli-
cations, features fully static operation requiring no external
clocks or timing strobes. The automatic power-down feature
reduces the power consumption by more than 70% when the
circuit is deselected. Easy memory expansion is provided by
an active-LOW Chip Enable (CE
able (CE
state drivers.
An active-LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
puts are both LOW, data on the nine data input/output pins
(I/O
dressed by the address present on the address pins (A
through A
the device and enabling the outputs, (CE
and CE
Under these conditions, the contents of the location addressed
by the information on address pins is present on the nine data
input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to insure alpha immunity.
0
through I/O
C182–1
2
2
active HIGH), while (WE) remains inactive or HIGH.
12
), an active-LOW Output Enable (OE), and three-
San Jose
). Reading the device is accomplished by selecting
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
8
8
7C182-35
) is written into the memory location ad-
140
Pin Configuration
35
35
GND
I/O
I/O
I/O
I/O
A
A
A
A
A
A
A
A
A
10
11
12
4
5
6
7
8
9
0
1
2
3
8Kx9 Static RAM
CA 95134
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DIP/SOJ
Top View
1
), an active HIGH Chip En-
Revised August 24, 2001
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
and OE active LOW
C182–2
7C182-45
V
WE
CE
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CY7C182
CC
3
2
1
0
8
7
6
5
4
2
1
140
408-943-2600
45
35
1
and WE in-
0
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CY7C182-25PC Summary of contents

Page 1

... Automatic power-down when deselected • Easy memory expansion with CE Functional Description The CY7C182 is a high-speed CMOS static RAM organized as 8,192 by 9 bits and it is manufactured using Cypress’s high- performance CMOS technology. Access times as fast are available with maximum power consumption of only 770 mW ...

Page 2

... IN IL MAX Max > V 0.3V > < 0.3V Test Conditions MHz 5. 481 5V 3. GND 255 < INCLUDING JIG AND C182–3 SCOPE (b) 1.73V CY7C182 Ambient Temperature 10% 7C182-25, 35, 45 Min. Max. Unit 2.4 V 0 0.5 0 +10 10 +10 300 mA 140 < 0.3V Max. Unit 10 ...

Page 3

... LOW, CE HIGH, and WE LOW. All three signals must be asserted to initiate a write less than t for any given device. These parameters are sampled and not 100% tested. LZWE HZWE transition HIGH. 2 CY7C182 7C182-35 7C182-45 Max. Min. Max. Unit ...

Page 4

... LOW simultaneously with WE HIGH, the output remains in a high-impedance state Document #: 38-05031 Rev OHA DOE DATA VALID 50 SCE1 t SCE2 PWE t SD DATA VALID t HZWE HIGH IMPEDANCE . IH. CY7C182 DATA VALID C182–5 t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB C182– LZWE C182–7 Page [+] Feedback ...

Page 5

... Ordering Information Speed (ns) Ordering Code 25 CY7C182 25PC CY7C182 25VC 35 CY7C182 35PC CY7C182 35VC 45 CY7C182 45PC CY7C182 45VC Document #: 38-05031 Rev SCE1 t SCE2 PWE t SD DATA VALID t HZWE Data In Data Out Z Z Deselect/Power-Down Z Valid Read Valid Z Write Z Z Output Disable Z Z Deselect ...

Page 6

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Molded SOJ V21 CY7C182 51-85014-B 51-85031-B Page ...

Page 7

... Document Title: CY7C182 Static RAM Document Number: 38-05031 Issue Orig. of REV. ECN NO. Date Change ** 106825 09/15/01 SZV Document #: 38-05031 Rev. ** Description of Change Change from Spec number: 38-00110 to 38-05031 CY7C182 Page [+] Feedback ...

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