CY7C056V-12AXC Cypress Semiconductor Corp, CY7C056V-12AXC Datasheet - Page 18

• Manufacturer Part Number: CY7C056V-12AXC
• Description: IC SRAM 576KBIT 12NS 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C056V-12AXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 576K (16K x 36)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Architecture
The CY7C056V and CY7C057V consist of an array of 16K and
32K words of 36 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE
control pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes/reads to the
same location, a BUSY pin is provided on each port. Two
Interrupt
communication. Two Semaphore (SEM) control pins are used for
allocating shared resources. With the M/S pin, the devices can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The devices also have an automatic
power-down feature controlled by CE
provided with its own Output Enable control (OE), which allows
data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE
waveform). Required inputs for non-contention operations are
summarized in
and the opposite port attempts to read that location, a port-to-port
flowthrough delay must occur before the data is read on the
output; otherwise the data read is not deterministic. Data will be
valid on the port t
port.
Read Operation
When reading the device, the user must assert both the OE and
CE
is asserted. If the user wishes to access a semaphore flag, then
the SEM pin must be asserted instead of the CE
must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (3FFF for the CY7C056V,
7FFF for the CY7C057V) is the mailbox for the right port and the
second-highest memory location (3FFE for the CY7C056V,
7FFE for the CY7C057V) is the mailbox for the left port. When
one port writes to the other port’s mailbox, an interrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.The operation of the interrupts and their interaction with
Busy are summarized in
Busy
The CY7C056V and CY7C057V provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
Document #: 38-06055 Rev. *E
[3]
pins. Data will be available t
(INT)
Table 1.
DDD
pins
0
after the data is presented on the other
If a location is being written to by one port
and CE
Table
can
2.
1
be
ACE
pins (see Write Cycle No. 2
utilized
after CE or t
SD
0
/CE
0
before the rising edge
/CE
1
, OE, R/W). These
1
for
. Each port is
[3]
DOE
pin, and OE
port-to-port
after OE
both ports’ Chip Enables are asserted and an address match
occurs within t
which port has access. If t
gain permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted t
address match or t
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
This will allow the device to interface to a master device with no
external components. Writing to slave devices must be delayed
until after the BUSY input has settled (t
the slave chip may begin a write cycle during a contention
situation. When tied HIGH, the M/S pin allows the device to be
used as a master and, therefore, the BUSY line is an output.
BUSY can then be used to send the arbitration outcome to a
slave.
Semaphore Operation
The CY7C056V and CY7C057V provide eight semaphore
latches, which are separate from the dual-port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for t
The semaphore value will be available t
rising edge of the semaphore write. If the left port was successful
(reads a 0), it assumes control of the shared resource, otherwise
(reads a 1) it assumes the right port has control and continues to
poll the semaphore. When the right side has relinquished control
of the semaphore (by writing a 1), the left side will succeed in
gaining control of the semaphore. If the left side no longer
requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches. For
normal semaphore access, CE
LOW. A CE active semaphore access is also available. The
semaphore may be accessed through the right port with
CE
LOW and asserting the Bus Size Select (SIZE) pin HIGH. The
semaphore may be accessed through the left port with
CE
A
in the same manner as a normal memory access. When writing
or reading a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an available semaphore, a 1 will appear
at the same semaphore address on the right port. That
semaphore can now only be modified by the port showing 0 (the
left port in this case). If the left port now relinquishes control by
writing a 1 to the semaphore, the semaphore will be set to 1 for
both ports. However, if the right port had requested the
semaphore (written a 0) while the left port had control, the right
port would immediately own the semaphore as soon as the left
port released it.
0–2
0R
0L
/CE
represents the semaphore address. OE and R/W are used
/CE
1L
1R
active by asserting all B
active by asserting the Bus Match Select (BM) pin
PS
Table 3
SOP
of each other, the busy logic will determine
BLC
before attempting to read the semaphore.
after CE is taken LOW.
shows sample semaphore operations.
PS
is violated, one port will definitely
[3]
must remain HIGH during SEM
0–3
BLC
Byte Select pins HIGH.
SWRD
0
is used. If a zero is
or t
CY7C056V
CY7C057V
+ t
BLA
Page 18 of 26
DOE
BLA
), otherwise,
after the
after an
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