M24C01-WMN6P STMicroelectronics, M24C01-WMN6P Datasheet - Page 15

• Manufacturer Part Number: M24C01-WMN6P
• Description: IC EEPROM 1KBIT 400KHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M24C01-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1K (128 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 128 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Memory Configuration: 128 X 8
• Clock Frequency: 400kHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Density: 1Kb
• Access Time (max): 900ns
• Frequency (max): 400KHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Supply Current: 2mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8558; M24C01-WMN6P

M24C16, M24C08, M24C04, M24C02, M24C01
3.6.3
Figure 9.
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in
can be used by the bus master.
The sequence, as shown in
●
●
●
First byte of instruction
with RW = 0 already
decoded by the device
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Table
Write cycle polling flowchart using ACK
15, but the typical time is shorter. To make use of this, a polling sequence
ReStart
Stop
NO
Figure
NO
Doc ID 5067 Rev 16
Start condition
Device select
addressing the
with RW = 0
in progress
operation is
Write cycle
Returned
memory
9, is:
ACK
Next
YES
Write operation
Write operation
Continue the
Data for the
YES
NO
and Receive ACK
Send Address
condition
Start
Random Read operation
Device select
Continue the
with RW = 1
YES
Device operation
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w
) is
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