M29F800DB55N6E

Manufacturer Part NumberM29F800DB55N6E
DescriptionIC FLASH 8MBIT 55NS 48TSOP
ManufacturerNUMONYX
M29F800DB55N6E datasheet
 

Specifications of M29F800DB55N6E

Format - MemoryFLASHMemory TypeFLASH - Nor
Memory Size8M (1M x 8 or 512K x 16)Speed55ns
InterfaceParallelVoltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°CPackage / Case48-TSOP
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Feature summary
Supply voltage
– V
= 5V ±10% for Program, Erase and
CC
Read
Access time: 55, 70, 90ns
Programming time
– 10µs per Byte/Word typical
19 Memory Blocks
– 1 Boot Block (Top or Bottom location)
– 2 Parameter and 16 Main Blocks
Program/Erase controller
– Embedded Byte/Word Program algorithms
Erase Suspend and Resume modes
– Read and Program another Block during
Erase Suspend
Unlock Bypass Program command
– Faster Production/batch Programming
Temporary Block Unprotection mode
Common Flash Interface
– 64 bit Security Code
Low power consumption
– Standby and Automatic Standby
100,000 Program/Erase cycles per Block
Electronic Signature
– Manufacturer Code: 0020h
– Top Device Code M29F800DT: 22ECh
– Bottom Device Code M29F800DB: 2258h
August 2006
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
5V Supply Flash Memory
Rev 5
M29F800DT
M29F800DB
SO44 (M)
TSOP48 (N)
12 x 20mm
1/53
www.st.com
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M29F800DB55N6E Summary of contents

  • Page 1

    ... Program/Erase cycles per Block Electronic Signature – Manufacturer Code: 0020h – Top Device Code M29F800DT: 22ECh – Bottom Device Code M29F800DB: 2258h August 2006 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) 5V Supply Flash Memory Rev 5 M29F800DT M29F800DB SO44 (M) TSOP48 ( 20mm 1/53 www ...

  • Page 2

    Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 3

    M29F800DT 4.0.9 4.0.10 4.0.11 4.0.12 5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 5

    M29F800DT List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    ... The M29F800D Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (5V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently possible to preserve valid data while old data is erased ...

  • Page 7

    M29F800DT Figure 1. Logic diagram Table 1. Signal names A0-A18 DQ0-DQ7 DQ8-DQ14 DQ15A– BYTE A0-A18 W M29F800DT E M29F800DB G RP BYTE V SS Address Inputs ...

  • Page 8

    Summary description Figure 2. SO connections 8/ A18 2 43 A17 ...

  • Page 9

    M29F800DT Figure 3. TSOP connections A15 1 48 A14 A13 A12 A11 A10 M29F800DT M29F800DB A18 A17 Summary ...

  • Page 10

    Summary description Figure 4. Block addresses (x8) M29F800DT Top Boot Block Addresses (x8) FFFFFh 16 KByte FC000h FBFFFh 8 KByte FA000h F9FFFh 8 KByte F8000h F7FFFh 32 KByte F0000h EFFFFh 64 KByte E0000h 1FFFFh 64 KByte 10000h 0FFFFh 64 KByte ...

  • Page 11

    M29F800DT Figure 5. Block addresses (x16) M29F800DT Top Boot Block Addresses (x16) 7FFFFh 8 KWord 7E000h 7DFFFh 4 KWord 7D000h 7CFFFh 4 KWord 7C000h 7BFFFh 16 KWord 78000h 77FFFh 32 KWord 70000h 0FFFFh 32 KWord 08000h 07FFFh 32 KWord 00000h ...

  • Page 12

    ... Figure 1: Logic connected to this device. 2.0.1 Address Inputs (A0-A18) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. 2.0.2 Data Inputs/Outputs (DQ0-DQ7) The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation ...

  • Page 13

    ... This prevents Bus Write operations from accidentally damaging the data LKO during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the V Ground pin to decouple the current surges from the power supply ...

  • Page 14

    ... Write, Output Disable, Standby and Automatic Standby. See = VIL, and Table 3: Bus operations, BYTE = VIH than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.0.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the Command Interface ...

  • Page 15

    ... Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require V 3.0.7 Electronic Signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in and Table 3: Bus operations, BYTE = 3 ...

  • Page 16

    ... Read/Reset command The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. ...

  • Page 17

    ... Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 4.0.4 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory ...

  • Page 18

    ... When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. 4.0.8 Block Erase command The Block Erase command can be used to erase a list of one or more blocks ...

  • Page 19

    ... Read CFI Query command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is ready to read the array data or when the device is in autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area ...

  • Page 20

    Command Interface Table 4. Commands, 16-bit mode, BYTE = V Command Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 Read/Reset 3 Auto Select 3 Program 4 Unlock Bypass 3 Unlock Bypass Program 2 Unlock Bypass ...

  • Page 21

    M29F800DT Table 5. Commands, 8-bit mode, BYTE = V Command Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 Read/Reset 3 AAA Auto Select 3 AAA Program 4 AAA Unlock Bypass 3 AAA Unlock Bypass 2 ...

  • Page 22

    ... DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’ ...

  • Page 23

    ... Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’ ...

  • Page 24

    Status Register Table 7. Status Register Bits Operation Program Program during Erase Suspend Program Error Chip Erase Block Erase before timeout Block Erase Erase Suspend Erase Error 1. Unspecified data bits should be ignored. Figure 6. Data Polling flowchart 24/53 ...

  • Page 25

    M29F800DT Figure 7. Data Toggle flowchart START READ DQ6 READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE DQ6 NO = TOGGLE YES FAIL PASS AI01370C Status Register 25/53 ...

  • Page 26

    Maximum rating 6 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are ...

  • Page 27

    M29F800DT 7 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the ...

  • Page 28

    DC and AC parameters Figure 9. AC measurement Load Circuit Table 10. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. 28/ DEVICE UNDER TEST 0.1µ includes JIG ...

  • Page 29

    M29F800DT Table 11. DC characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Read) CC1 I Supply Current (Standby) TTL CC2 I Supply Current (Standby) CMOS CC3 (1) I Supply Current (Program/Erase) CC4 ...

  • Page 30

    DC and AC parameters Table 12. Read AC characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC ( Chip Enable Low to Output Transition ELQX ...

  • Page 31

    M29F800DT Figure 11. Write AC waveforms, Write Enable controlled A0-A18/ A– DQ0-DQ7/ DQ8-DQ15 tAVAV VALID tAVWL tELWL tGHWL tWLWH tVCHEL DC and AC parameters tWLAX tWHEH tWHGL tWHWL tDVWH tWHDX VALID tWHRL AI06155 31/53 ...

  • Page 32

    DC and AC parameters Table 13. Write AC characteristics, Write Enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV Chip Enable Low to Write Enable Low ELWL Write Enable Low ...

  • Page 33

    M29F800DT Table 14. Write AC characteristics, Chip Enable controlled Symbol Alt t t AVAV WLEL ELEH DVEH EHDX EHWH EHEL CPH t ...

  • Page 34

    DC and AC parameters Table 15. Reset/Block Temporary Unprotect AC characteristics Symbol ( PHWL PHEL (1) t PHGL (1) t RHWL (1) t RHEL (1) t RHGL t PLPX (1) t PLYH (1) t PHPHH 1. Sampled only, ...

  • Page 35

    M29F800DT 8 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the ...

  • Page 36

    Package mechanical Figure 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, package outline b 1. Drawing is not to scale. Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, package mechanical data ...

  • Page 37

    M29F800DT Figure 15. TSOP48 – 48 lead Plastic Thin Small Outline 20mm, package outline DIE 1. Drawing is not to scale. Table 17. TSOP48 – 48 lead Plastic Thin Small Outline 20mm, package ...

  • Page 38

    Part numbering 9 Part numbering Table 18. Ordering information scheme Example: Device Type M29 Operating Voltage ± 10% CC Device Function 800D = 8 Mbit (x8/x16), Boot Block Array Matrix T = Top Boot B ...

  • Page 39

    ... M29F800DT Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Part numbering 39/53 ...

  • Page 40

    Block address table Appendix A Block address table T Table 19. Top Boot Block addresses, M29F800D # Size (Kbytes ...

  • Page 41

    M29F800DT Table 20. Bottom Boot Block addresses, M29F800DB # Size (Kbytes ...

  • Page 42

    ... Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...

  • Page 43

    M29F800DT Table 22. CFI Query Identification String Address x16 x8 10h 20h 11h 22h 12h 24h 13h 26h 14h 28h 15h 2Ah 16h 2Ch 17h 2Eh 18h 30h 19h 32h 1Ah 34h 1. Query data are always presented on the ...

  • Page 44

    Common Flash Interface (CFI) Table 24. Device Geometry Definition Address x16 x8 27h 4Eh 28h 50h 29h 52h 2Ah 54h 2Bh 56h 2Ch 58h 2Dh 5Ah 2Eh 5Ch 2Fh 5Eh 30h 60h 31h 62h 32h 64h 33h 66h 34h 68h ...

  • Page 45

    M29F800DT Table 25. Primary Algorithm-specific Extended Query table Address Data x16 x8 40h 80h 0050h 41h 82h 0052h 42h 84h 0049h 43h 86h 0031h Major version number, ASCII 44h 88h 0030h Minor version number, ASCII 45h 8Ah 0000h 46h 8Ch ...

  • Page 46

    ... Signal Descriptions section. Unlike the Command Interface of the Program/Erase Controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. For example, the techniques for AMD parts will not work on STMicroelectronics parts. Care should be taken when changing drivers for one part to work on another. ...

  • Page 47

    M29F800DT Table 27. Programmer technique bus operations, BYTE = V Operation E G Block Protect Chip Unprotect Block Protection verify Block Unprotection verify Address ...

  • Page 48

    Block protection Figure 16. Programmer Equipment Block Protect flowchart 48/53 START ADDRESS = BLOCK ADDRESS Wait 4µ Wait 100µs ...

  • Page 49

    M29F800DT Figure 17. Programmer Equipment Chip Unprotect flowchart START PROTECT ALL BLOCKS CURRENT BLOCK = 0 A6, A12, A15 = Wait 4µ Wait 10ms ...

  • Page 50

    Block protection Figure 18. In-System Equipment Block Protect flowchart 50/53 START WRITE 60h ADDRESS = BLOCK ADDRESS WRITE 60h ...

  • Page 51

    M29F800DT Figure 19. In-System Equipment Chip Unprotect flowchart ISSUE READ/RESET START PROTECT ALL BLOCKS CURRENT BLOCK = WRITE 60h ANY ADDRESS WITH ...

  • Page 52

    Revision history Revision history Table 28. Document revision history Date Revision 13-Dec-2001 21-Jan-2002 01-Mar-2002 17-Feb-2003 08-Jul-2003 24-Aug-2006 52/53 -01 First Issue -02 V (max) value corrected IH Description of Ready/Busy signal clarified (and Temporary Unprotect AC waveforms -03 Clarified allowable ...

  • Page 53

    M29F800DT Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...