M25P05-AVMB6TP NUMONYX, M25P05-AVMB6TP Datasheet - Page 50

• Manufacturer Part Number: M25P05-AVMB6TP
• Description: IC FLASH 512KBIT 50MHZ 8MLP
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMB6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P05-AVMB6TPCT

Revision history
13
50/52
Revision history
Table 23.
25-Feb-2001
12-Sep-2002
13-Dec-2002
24-Nov-2003
01-Aug-2005
19-Dec-2006
11-Apr-2002
13-Jan-2005
01-Apr-2005
06-Jul-2006
Date
Document revision history
Revision
1.0
1.1
1.2
1.3
2
3
4
5
6
7
Initial release.
Clarification of descriptions of entering Standby Power mode from Deep
Power-down mode, and of terminating an instruction sequence or data-
out sequence.
VFQFPN8 package (MLP8) added.
Typical Page Program time improved. Write Protect setup and hold times
specified, for applications that switch Write Protect to exit the Hardware
Protection mode immediately before a WRSR, and to enter the Hardware
Protection mode again immediately after.
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added.
40 MHz AC characteristics table included as well as 25 MHz. I
t
package
Devices with process technology code X added
(RDID)
TSSOP8 package added.
Notes 1 and 2 removed from
Note 1 added.
Note 1 to
values removed.
Small text changes.
Frequency test condition modified for I
Read identification
deep power-down and read electronic signature (RES)
Active power, standby power and deep power-down modes
clarified.
SO8 package specifications updated (see
Updated Page Program (PP) instructions in
program (PP)
Packages are fully ECOPACK® compliant. SO8N and VFQFPN8 package
specifications updated (see
Figure 3: Bus master and memory devices on the SPI bus
Note 2
ratings. Small text changes.
VCC supply voltage
master and memory devices on the SPI bus
replaced by explanatory paragraph.
WIP bit behavior at power-up specified in
down. T
ratings. VFQFPN8 and SO8N packages updated (see
Package
SE
(typ) and t
added. T
and
LEAD
mechanical).
Table 9: Absolute maximum ratings
Table 17: AC characteristics (50 MHz
BE
added and V
and
(typ) values improved. Change of naming for VDFPN8
LEAD
Instruction
(RDID),
and
removed from
VSS ground
IO
Deep power-down (DP)
Section 11: Package
max modified in
Table 22: Ordering information scheme
times.
Changes
Section Table 9.: Absolute maximum
descriptions added.
CC3
Section 7: Power-up and power-
in
Figure 26.
Page
Table 13: DC
updated, note 2 removed
Table 9: Absolute maximum
changed, note 2 and T
(Read identification
mechanical).
operation)) added.
programming,
and
and
Section 11:
instructions and
Release from
Table
characteristics.
Figure 3: Bus
updated and
paragraph
CC3
M25P05-A
18).
Page
(max),
LEAD
and