M25PE10-VMP6TG NUMONYX, M25PE10-VMP6TG Datasheet - Page 45

• Manufacturer Part Number: M25PE10-VMP6TG
• Description: IC FLASH 1MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE10-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PE10-VMP6TGCT

M25PE20, M25PE10
7
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
●
●
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while V
power on reset (POR) threshold value, V
does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of t
elapsed after the moment that V
operation of the device is not guaranteed if, by this time, V
write, program or erase instructions should be sent until the later of:
●
●
These values are specified in
If the delay, t
selected for read instructions even if the t
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the power-up and power-down phases.
At power-up, the device is in the following state:
●
●
●
●
Normal precautions must be taken for supply rail decoupling, to stabilize the V
Each device in a system should have the V
the package pins. (Generally, this capacitor is of the order of 100 nF).
At power-down, when V
(POR) threshold voltage, V
to any instruction. The designer needs to be aware that if a power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.
V
V
t
t
The device is in the Standby Power mode (not the Deep Power-down mode)
The Write Enable Latch (WEL) bit is reset
The Write In Progress (WIP) bit is reset
The Lock Registers are reset (Write Lock bit, Lock Down bit) = (0, 0).
PUW
VSL
CC
SS
(min) at power-up, and then for a further delay of t
at power-down
after V
after V
VSL
, has elapsed, after V
CC
CC
passed the V
passed the V
CC
WI
drops from the operating voltage, to below the power on reset
, all operations are disabled and the device does not respond
Table
CC
CC
CC
) until V
WI
Section 3: SPI
(min) level
rises above the V
13.
threshold
CC
WI
has risen above V
CC
PUW
CC
– all operations are disabled, and the device
reaches the correct value:
rail decoupled by a suitable capacitor close to
delay is not yet fully elapsed.
modes.
WI
threshold. However, the correct
CC
VSL
CC
is still below V
(min), the device can be
Power-up and power-down
CC
CC
is less than the
CC
(min). No
PUW
supply.
has
45/64