TC55VBM316AFTN55 Toshiba, TC55VBM316AFTN55 Datasheet
TC55VBM316AFTN55
Specifications of TC55VBM316AFTN55
TC55W800FT-55M
TC55W800FT5(M)
TC55W800FT5(MWR)
TC55W800FT5(Y)
TC55W800FT55(M)
TC55W800FT55(MWR)
TC55W800FT55M
TC55W800FT55MLA
TC55W800FT5M
TC55W800FT5M
TC55W800FT5Y
TC55W800FT5Y
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Related parts for TC55VBM316AFTN55
TC55VBM316AFTN55 Summary of contents
Page 1
... The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by 16 bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time ...
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... I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 CE 1 CE2 LB UB R/W OE BYTE TC55VBM316AFTN/ASTN40,55 MEMORY CELL ARRAY 4,096 128 16 (8,388,608) SENSE AMP COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER CLOCK GENERATOR A GND ...
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OPERATING MODE MODE CE 1 CE2 Read Write Output ...
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DC CHARACTERISTICS (Ta SYMBOL PARAMETER Input Leakage Current I Output High Current Output Low Current V OL Output Leakage Current R/W CE R/W l DDO1 I OUT Other Input Operating Current ...
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AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta 40° to 85°C, V 2 READ CYCLE SYMBOL t Read Cycle Time RC t Address Access Time ACC t Chip Enable Access Time 1 CO1 t Chip Enable(CE2) ...
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AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta 40° to 85°C, V 2 READ CYCLE SYMBOL t Read Cycle Time RC t Address Access Time ACC t Chip Enable Access Time 1 CO1 t Chip Enable(CE2) ...
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AC TEST CONDITIONS PARAMETER Input pulse level Timing measurements Reference level Output load Fig.1 : Input rise and fall time V Typ DD 90% 10% GND 1 V/ BYTE FUNCTION SYMBOL t BYTE ...
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Note 1) READ CYCLE Address A0~A18 (Word Mode) A-1~A18 (Byte Mode CE2 OUT I/O1~16 (Word Mode) Hi-Z I/O1~8 (Byte Mode) WRITE CYCLE 1 (R/W CONTROLLED) Address A0~A18 (Word Mode) A-1~A18 (Byte Mode) ...
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WRITE CYCLE 2 ( CE1 CONTROLLED) Address A0~A18 (Word Mode) A-1~A18 (Byte Mode) R CE2 OUT I/O1~16 (Word Mode) I/O1~8 (Byte Mode I/O1~16 (Word Mode) I/O1~8 (Byte Mode) WRITE CYCLE 3 (CE2 ...
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WRITE CYCLE Address A0~A18 (Word Mode) R CE2 OUT I/O1~16 (Word Mode I/O1~16 (Word Mode) Note: (1) R/W remains HIGH for the read cycle. (2) If CE1 ...
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DATA RETENTION CHARACTERISTICS ( SYMBOL V Data Retention Supply Voltage DH I Standby Current DDS2 t Chip Deselect to Data Retention Mode Time CDR t Recovery Time R CE1 CONTROLLED DATA RETENTION MODE 2 ...
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Note: (1) In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 0 CE2 V 0 (2) When CE1 is operating at the V transition of V from 2.3(2.7) to 2.2V(2.4 V). ...
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PACKAGE DIMENSIONS TSOP Ⅰ 48-P-1220-0. Weight:0.51 g (typ) TC55VBM316AFTN/ASTN40,55 18.4 0.1 20.0 0.2 Unit: 1.0 0.1 0.1 0.05 1.2max 0.5 0.1 2002-08-05 13/15 ...
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PACKAGE DIMENSIONS TSOP Ⅰ 48-P-1214-0. Weight:0.36 g (typ) TC55VBM316AFTN/ASTN40, 12.4 0.1 14.0 0.2 Unit:mm 1.0 0.1 0.1 0.05 1.2max 0.5 0.1 2002-08-05 14/15 ...
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... TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property ...