MD4811-D512-V3Q18-X-P/Y SanDisk, MD4811-D512-V3Q18-X-P/Y Datasheet - Page 74

• Manufacturer Part Number: MD4811-D512-V3Q18-X-P/Y
• Description: IC MDOC G3 512MB 48-TSOP
• Manufacturer: SanDisk

Specifications of MD4811-D512-V3Q18-X-P/Y

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 512M (64M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1136

9.5
9.5.1 Hardware Configuration
To configure the hardware for working with the interrupt mechanism, connect the IRQ# pin/ball to
the host interrupt input.
Note: A nominal 10 KΩ pull-up resistor must be connected to this pin/ball.
9.5.2
Configuring the software to support the IRQ# interrupt is performed in two stages.
Stage 1
Configure the software so that when the system is initialized, the following steps occur:
1.
2.
3.
4.
Stage 2
Configure the software so that for every long flash I/O operation, the following steps occur:
1.
2.
3.
4.
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The correct value is written to the Interrupt Control register to configure Mobile DiskOnChip
G3 for:
•
•
Note: Refer to Section 7 for further information on the value to write to this register.
The host interrupt is configured to the selected input sensitivity, either edge or level-triggered.
The handshake mechanism between the interrupt handler and the OS is initialized.
The interrupt service routine to the host interrupt is connected and enabled.
The correct value is written to the Interrupt Control register to enable the IRQ# interrupt.
Note: Refer to Section 7 for further information on the value to write to this register.
The flash I/O operation starts.
Control is returned to the OS to continue other tasks. When the IRQ# interrupt is received,
other interrupts are disabled and the OS is flagged.
The OS either returns control immediately to the TrueFFS driver, or waits for the appropriate
condition to return control to the TrueFFS driver.
Implementing the Interrupt Mechanism
Software Configuration
Interrupt source: Flash ready, data protection, last byte during DMA has been transferred,
or BCH ECC error has been detected (used during multi-page DMA operations).
Output sensitivity: Either edge or level-triggered
Preliminary Data Sheet, Rev. 1.1
Mobile DiskOnChip G3
91-SR-011-05-8L