MD4832-D512-V3Q18-X/Y SanDisk, MD4832-D512-V3Q18-X/Y Datasheet - Page 7

• Manufacturer Part Number: MD4832-D512-V3Q18-X/Y
• Description: IC MDOC G3 512MB 85-FBGA
• Manufacturer: SanDisk

Specifications of MD4832-D512-V3Q18-X/Y

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 512M (64M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 585-1140

8. Booting from Mobile DiskOnChip G3 .................................................................................... 64
9. Design Considerations ........................................................................................................... 67
4
7.8
7.9
7.10 Configuration Register...................................................................................................... 56
7.11 Interrupt Control Register ................................................................................................. 57
7.12 Interrupt Status Register................................................................................................... 58
7.13 Output Control Register.................................................................................................... 59
7.14 DPD Control Register ....................................................................................................... 60
7.15 DMA Control Register [1:0]............................................................................................... 61
7.16 MultiBurst Mode Control Register..................................................................................... 63
8.1
8.2
8.3
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
DiskOnChip Control Register/Control Confirmation Register ........................................... 55
Device ID Select Register................................................................................................. 56
Introduction....................................................................................................................... 64
Boot Procedure in PC-Compatible Platforms ................................................................... 64
Boot Replacement ............................................................................................................ 65
8.3.1
8.3.2
8.3.3
General Guidelines........................................................................................................... 67
Standard NOR-Like Interface ........................................................................................... 68
Multiplexed Interface ........................................................................................................ 69
Connecting Control Signals .............................................................................................. 69
9.4.1
9.4.2
Implementing the Interrupt Mechanism ............................................................................ 71
9.5.1
9.5.2
Device Cascading............................................................................................................. 72
Boot Replacement ............................................................................................................ 73
Platform-Specific Issues ................................................................................................... 74
9.8.1
9.8.2
9.8.3
9.8.4
Design Environment ......................................................................................................... 76
PC Architectures ................................................................................................................ 65
Non-PC Architectures......................................................................................................... 66
Asynchronous Boot Mode .................................................................................................. 66
Standard Interface.............................................................................................................. 69
Multiplexed Interface .......................................................................................................... 70
Hardware Configuration ..................................................................................................... 71
Software Configuration....................................................................................................... 71
Wait State ........................................................................................................................... 74
Big and Little Endian Systems............................................................................................ 74
Busy Signal......................................................................................................................... 74
Working with 8/16/32-Bit Systems...................................................................................... 74
Preliminary Data Sheet, Rev. 1.1
Mobile DiskOnChip G3
91-SR-011-05-8L