DS3050W-100# Maxim Integrated Products, DS3050W-100# Datasheet - Page 12

• Manufacturer Part Number: DS3050W-100#
• Description: IC NVSRAM 4MBIT 100NS 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3050W-100#

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 4M (512K x 8)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3V Single-Piece 4Mb Nonvolatile SRAM
with Clock
The DS3050W executes an SRAM read cycle whenever
CS (RTC chip select) and WE (write enable) are inactive
(high) and CE (SRAM chip enable) is active (low). The
unique address specified by the 19 address inputs (A0
to A18) defines which of the 524,288 bytes of SRAM data
is to be accessed. Valid data will be available to the
eight data output drivers within t
the last address input signal is stable, providing that CE
and OE (output enable) access times are also satisfied.
If CE and OE access times are not satisfied, then data
access must be measured from the later occurring sig-
nal (CE or OE) and the limiting parameter is either t
CE or t
Table 2. RTC Register Map
x = Don’t care address bits.
X = Unused. Read/writeable under write and read bit control.
FT = Frequency test bit.
OSC = Oscillator start/stop bit.
W = Write bit.
R = Read bit.
WDS = Watchdog steering bit.
BMB0–BMB4 = Watchdog multiplier bits.
RB0, RB1 = Watchdog resolution bits.
12
ADDRESS
xxxxDh
xxxxCh
xxxxFh
xxxxEh
xxxxBh
xxxxAh
xxxx9h
xxxx8h
xxxx7h
xxxx6h
xxxx5h
xxxx4h
xxxx3h
xxxx2h
xxxx1h
xxxx0h
____________________________________________________________________
OE
for OE rather than address access.
WDS
OSC
AM4
AM3
AM2
AM1
WF
B7
AE
W
X
X
X
X
X
Y
BMB4
B6
AF
FT
X
X
X
R
Y
Y
Y
Y
10 YEAR
10 SECONDS
10 SECONDS
10 MINUTES
10 MINUTES
ACC
SRAM Read Mode
BMB3
ABE
B5
10 CENTURY
X
X
Y
0
10 HOURS
(access time) after
10 HOUR
10 DATE
10 DATE
BMB2
10 M
BLF
B4
X
Y
Y
DATA
CO
for
BMB1
B3
X
Y
Y
0
AE = Alarm flag enable.
Y = Unused. Read/writeable without write and read bit control.
ABE = Alarm in backup mode enable.
AM1–AM4 = Alarm mask bits.
WF = Watchdog flag.
AF = Alarm flag.
0 = Reads as a 0 and cannot be changed.
BLF = Battery low flag.
The DS3050W executes an SRAM write cycle whenever
CS is inactive (high) and the CE and WE signals are
active (low) after address inputs are stable. The later-
occurring falling edge of CE or WE determines the start of
the write cycle. The write cycle is terminated by the earlier
rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the
high state for a minimum recovery time (t
another cycle can be initiated. The CS and OE control
signal should be kept inactive (high) during SRAM write
cycles to avoid bus contention. However, if the output dri-
vers have been enabled (CE and OE active) then WE dis-
ables the outputs in t
BMB0
B2
Y
Y
0
SECONDS
SECONDS
CENTURY
MINUTES
MINUTES
MONTH
HOURS
HOUR
YEAR
DATE
DATE
RB1
B1
DAY
Y
Y
0
ODW
RB0
B0
Y
Y
0
from its falling edge.
Clock Operations
ALARM DATE
INTERRUPTS
WATCHDOG
SECONDS
CONTROL
SECONDS
MINUTES
MINUTES
UNUSED
MONTH
ALARM
HOURS
ALARM
ALARM
SRAM Write Mode
FLAGS
HOUR
FUNCTION/RANGE
YEAR
DATE
DAY
WR
00–99
01–12
01–31
01–07
00–23
00–59
00–59
00–39
01–31
00–23
00–59
00–59
) before
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