CAT24C256WI-GT3 ON Semiconductor, CAT24C256WI-GT3 Datasheet
CAT24C256WI-GT3
Specifications of CAT24C256WI-GT3
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CAT24C256WI-GT3 Summary of contents
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... Supports Standard, Fast and Fast−Plus I • 1 5.5 V Supply Voltage Range • 64−Byte Page Write Buffer • Hardware Write Protection for Entire Memory • Schmitt Triggers and Noise Suppression Filters on I (SCL and SDA) • Low Power CMOS Technology • ...
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Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is ...
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Table 5. A.C. CHARACTERISTICS ( −40°C to +125°C, and Symbol Parameter F Clock Frequency SCL t START Condition Hold Time HD:STA t Low Period of SCL Clock LOW t ...
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Power-On Reset (POR) The CAT24C256 Die Rev. C incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after V exceeds the POR trigger level ...
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SCL SDA START CONDITION BUS RELEASE DELAY (TRANSMITTER) SCL FROM 1 MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START LOW SCL t SU:STA t HD:STA SDA IN SDA OUT Figure 2. Start/Stop Timing 1 0 ...
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... The CAT24C256 will not acknowledge the Slave address, as long as internal Write is in progress. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C256. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9) ...
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BUS ACTIVITY: SLAVE R MASTER ADDRESS T SDA LINE Don’t Care Bit SCL SDA 8th Bit Byte n S BUS T ACTIVITY: A SLAVE MASTER R ADDRESS A − SDA ...
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... If the Master acknowledges the 1st data byte transmitted by the CAT24C256, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 12). If the end of memory is reached during sequential Read, then the address counter will ‘wrap−around’ to the beginning of memory, etc. Sequential Read works with either ‘ ...
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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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D E PIN #1 IDENTIFICATION TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.25 0.30 D 2.90 3.00 D2 0.90 1.00 E 4.80 4.90 E2 0.90 1.00 e 0.65 TYP ...
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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...
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D E PIN #1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.45 0.50 A1 0.00 0.02 A3 0.127 REF b 0.20 0.25 D 1.95 2.00 D2 1.35 1.40 E 2.95 3.00 E2 1.25 1.30 e 0.50 REF L 0.25 ...
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E E1 TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD−01 ISSUE O SYMBOL MIN A A1 ...
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... The standard lead finish is NiPdAu. 12. The device used in the above example is a CAT24C256WI−GT3 (SOIC−JEDEC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 13. For SOIC, EIAJ (X) package the standard lead finish is Matte−Tin. This package is available in 2,000 pcs/reel, i.e., CAT24C256XI−T2. ...