XC17V16VQ44I Xilinx Inc, XC17V16VQ44I Datasheet - Page 3

• Manufacturer Part Number: XC17V16VQ44I
• Description: IC PROM SER I-TEMP 3.3V 44-VQFP
• Manufacturer: Xilinx Inc

Specifications of XC17V16VQ44I

• Programmable Type: OTP
• Memory Size: 16Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Description
DATA[0:7]
The array data value corresponding to the internal address
counter location is output on enabled DATA[0-7] output
pin(s) when CE is active, OE is active, and the internal
address counter has not incremented beyond its Terminal
Count (TC) value. Otherwise, all data pins are in a high
impedance state when CE is inactive, OE is inactive, or the
internal address counter has incremented beyond its
Terminal Count (TC) value.
The XC17V01, XC17V02, and XC17V04 have only the
single DATA output pin for connection to the FPGA serial
configuration data input pin.
The XC17V08 and XC17V16 have the D[0-7] output pins.
During device programming, the XC17V08 and XC17V16
must be programmed for use in either serial output mode or
parallel output mode. For XC17V08 and XC17V16 devices
programmed to serial output mode, only the D0 pin is
enabled for data output to the Virtex
configuration data input pin. In serial mode, the D[1-7]
output pins remain in high impedance state and may be
unconnected. For XC17V08 and XC17V16 devices
programmed to parallel output mode, all D[0-7] output pins
are enabled for byte-wide data output to the FPGA
SelectMAP configuration data input pins.
The DATA/D0 pin is a bidirectional I/O during device
programming.
CLK
Each rising edge on the CLK input increments the internal
address counter, when CE is active, OE is active, the
internal address counter has not incremented past its
Terminal Count (TC) value, and BUSY is Low.
Note:
XC17V16.
RESET/OE
The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. The polarity is set at the time of
device programming. The device default is active-High
RESET, but compatibility with Xilinx FPGAs requires the
polarity to be programmed with an active-Low RESET.
When RESET is active, the address counter is held at “0”,
and puts the DATA output in a high-impedance state.
CE
When High, this pin holds the internal address counter in
reset, puts the DATA output in a high-impedance state, and
forces the device into low-I
DS073 (v1.12) November 13, 2008
Product Specification
The BUSY condition applies to only the XC17V08 and
R
CC
standby mode.
®
series FPGA serial
www.xilinx.com
CEO
Chip Enable Output is connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE
and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. CEO returns to High when OE goes inactive or
CE goes High.
BUSY (XC17V16 and XC17V08 Only)
Asserting the BUSY input High prevents rising edges on
CLK from incrementing the internal address counter and
maintains current data on the data pins.
Note:
to internally tie BUSY to an internal pull-down resistor must be set
during device programming.
V
Programming voltage. No overshoot above the specified
maximum voltage is permitted on this pin. For normal read
operation, this pin must be connected to V
so may lead to unpredictable, temperature-dependent
operation and severe problems in circuit debugging.
V
Positive supply and ground pins.
PROM Pinouts for XC17V16 and XC17V08
Pins not listed in
Table 1: Pinouts for XC17V16 and XC17V08
BUSY
D0
D1
D2
D3
D4
D5
D6
D7
CLK
RESET/OE
(OE/RESET)
CE
GND
CEO
PP
CC
Pin Name
Caution! Do not leave V
and GND
If the BUSY pin is floating, then the programmable option
44-pin VQFP (VQ44)
Table 1
XC17V00 Series Configuration PROMs
6, 18, 28, 37, 41
24
40
29
42
27
25
14
19
43
13
15
21
are “no connect.”
9
PP
floating!
44-pin PLCC (PC44)
3, 12, 24, 34, 43
CC
. Failure to do
(1)
30
35
33
15
31
20
25
19
21
27
2
4
5
3