NCP1218AD65R2G ON Semiconductor, NCP1218AD65R2G Datasheet - Page 14

• Manufacturer Part Number: NCP1218AD65R2G
• Description: IC PWM CONTROLLER 65KHZ 7-SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1218AD65R2G

• Output Isolation: Isolated
• Frequency Range: 61.8 ~ 68.3kHz
• Voltage - Input: 9 ~ 20 V
• Power (watts): 920mW
• Operating Temperature: 0°C ~ 150°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width) 7 leads
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Current−Mode Pulse Width Modulation
width modulation controller with ramp compensation. The
PWM block of the NCP1218 is shown in Figure 30. The
DRV signal is enabled by a clock pulse. At this time,
current begins to flow in the power MOSFET and the sense
resistor. A corresponding voltage is generated on the CS
pin of the device, ranging from very low to as high as the
maximum modulation voltage, V
This sets the primary current on a cycle−by−cycle basis.
Equation 3 gives the maximum drain current, I
where R
the current sense voltage threshold.
The NCP1218 is a current−mode, fixed frequency pulse
t
Figure 29. Soft−Start (Time = 0 at V
t
t
SSTART
SSTART
SSTART
Soft−start voltage, V
time must be less than t
to prevent fault condition
Drain Current, I
Pulse Width Modulation voltage, V
Feedback pin voltage divided by 3, V
CS
is the current sense resistor value and V
D
I
D(MAX)
SSTART
OVLD
+
V
R
ILIM
PWM
CS
PWM
1 V
(maximum of 1 V).
FB
CC
/3
= V
1 V
CC(on)
D(MAX)
http://onsemi.com
ILIM
(eq. 3)
1 V
time
time
time
)
time
is
,
14
current−mode pulse width modulation operation. An
internal clock sets the output RS latch, pulling the DRV pin
high. The latch is then reset when the voltage on the CS pin
intersects the modulation voltage, V
the duty ratio of the DRV pulse. The maximum duty ratio
is internally limited to 80% (typical) by the output RS latch.
pin voltage. The scale factor, I
is provided by an external error amplifier, whose output is
a function of the power supply output. An FB signal
between V
controller output. The FB voltage operates in a closed loop
with the output voltage to regulate the power supply.
placed as close to the FB pin as possible to improve the
noise immunity.
PWM
Output
Figure 31 shows the timing diagram for the
The V
It is recommended that an external filter capacitor be
Figure 31. Current−Mode Timing Diagram
Figure 30. Current−Mode Implementation
PWM
skip
80%
max duty
Q
voltage is the scaled representation of the FB
and 3 V determines the duty ratio of the
R
S
Clock
(1 V max. signal)
+
−
V
PWM
180 ns
ratio
LEB
I
ramp(peak)
, is 3. The FB pin voltage
V
PWM
CS
. This generates
I
clock
PWM
Output
V
ramp
CS
CS
V
PWM
R
CS
V
bulk
I
D