NCP1218AD65R2G ON Semiconductor, NCP1218AD65R2G Datasheet - Page 16

• Manufacturer Part Number: NCP1218AD65R2G
• Description: IC PWM CONTROLLER 65KHZ 7-SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1218AD65R2G

• Output Isolation: Isolated
• Frequency Range: 61.8 ~ 68.3kHz
• Voltage - Input: 9 ~ 20 V
• Power (watts): 920mW
• Operating Temperature: 0°C ~ 150°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width) 7 leads
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Gate Drive
drive the gate of an n−channel power MOSFET. The DRV
pin is capable of sourcing 500 mA and sinking 800 mA of
drive current. It has typical rise and fall times of 30 ns and
20 ns, respectively, driving a 1 nF capacitive load.
the capacitance of the power MOSFET must be considered
when calculating the NCP1218 power dissipation. The
driver power dissipation can be calculated using
Equation 8,
where Q
External Latch Input
incorporated using external circuits to suit a specific
application. An external fault condition can be used to
disable the controller by bringing the voltage on the
Skip/latch pin above the latch threshold, V
typical). When an external fault condition is detected, the
DRV signal is stopped, and the controller enters low current
operation mode. The external capacitor C
and V
voltage startup circuit turns on and I
V
V
removed from the HV pin, disabling the startup current and
allowing C
controller is reset by unplugging the power supply from the
wall to allow V
timing diagram of V
CC(on)
CC(hiccup)
The output drive of the NCP1218 is designed to directly
The power dissipation of the output stage while driving
Board
Oscillator Frequency
Figure 34. Oscillator Frequency Modulation
CC
G
is reached. V
is the gate charge of the power MOSFET.
drops until V
level
CC
until V
to discharge to V
bulk
P
DRV
CC
protection
to discharge. Figure 35 illustrates the
11.5 ms
CC
reaches V
+ f
CC
in the latch−off condition.
CC(hiccup)
OSC
cycles between V
@ Q
functionality
CC(reset)
CC(reset)
G
is reached. The high
@ V
start
CC
. Voltage must be
charges C
. Therefore, the
CC
f
f
f
OSC
OSC
OSC
latch
CC(on)
discharges
is
+ 11%
− 11%
CC
time
(3.9 V
http://onsemi.com
(eq. 8)
often
until
and
16
implement different kinds of latching protection. Figure 36
shows an example circuit in which a bipolar transistor is
used to pull the Skip/latch pin above the latch threshold.
The R
exceeding the maximum rated voltage. The NCP1219
applications note (AND8393/D) details several simple
circuits to implement overtemperature protection (OTP)
and overvoltage protection (OVP).
caused by noise from latching the part. However, it is
recommended that an external filter capacitor be placed as
close as possible to the Skip/latch pin to further improve the
noise immunity.
Startup current source is
charging the V
Fault
output
V
Startup current source turns
on when V
The external latch feature allows the circuit designers to
An internal blanking filter prevents fast voltage spikes
V
CC(hiccup)
CC(on)
LIM
Figure 35. Latch−off V
Figure 36. Circuit Example of an External
C
value is chosen to prevent the Skip/latch pin from
CC
skip
CC
reaches V
R
capacitor
LIM
V
R
Latch−off Circuit
CC
skip
CC(hiccup)
Startup current source is
off when V
CC
Timing Diagram
Skip/latch
GND
FB
CS
CC
is V
NCP1218
CC(on)
VCC
DRV
HV
time