ADE7763ARS Analog Devices Inc, ADE7763ARS Datasheet - Page 33

• Manufacturer Part Number: ADE7763ARS
• Description: IC ENERGY METER 1PHASE 20SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7763ARS

• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7763ZEB - BOARD EVALUATION FOR ADE7763
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Integration Times under Steady Load
As mentioned in the last section, the discrete time sample
period ( T ) for the accumulation register is 1.1 μs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
VAGAIN register set to 0x000, the average word value from the
apparent power stage is 0xA D055. The maximum value that
can be stored in the apparent energy register before it overflows
is 2
internal register, which can store 2
before it overflows. Therefore, the integration time under these
conditions with VADIV = 0 is calculated as follows:
When VADIV is set to a value other than 0, the integration time
varies, as shown in Equation 29.
LINE APPARENT ENERGY ACCUMULATION
The ADE7763 is designed with a special apparent energy
accumulation mode, which simplifies the calibration process.
24
Time = Time
Time
or 0xFF FFFF. The average word value is added to the
=
0xFFFF
CHANNEL 2
0xAD055
WDIV = 0
FROM
FFFF
ADC
× VADIV
FFFF
LPF1
×
1
48
2 .
or 0xFFFF FFFF FFFF
μ
s
ZERO-CROSSING
=
APPARENT
DETECTION
888
POWER
s
=
12
.
Figure 68. Apparent Energy Calibration
52
VADIV[7:0]
min
%
LINECYC[15:0]
CALIBRATION
CONTROL
(29)
Rev. B | Page 33 of 56
(28)
+
+
By using the on-chip zero-crossing detection, the ADE7763
accumulates the apparent power signal in the LVAENERGY
register for an integral number of half cycles, as shown in
Figure 68. The line apparent energy accumulation mode is
always active.
The number of half line cycles is specified in the LINECYC
register, which is an unsigned, 16-bit register. The ADE7763 can
accumulate apparent power for up to 65,535 combined half
cycles. Because the apparent power is integrated on the same
integral number of line cycles as the line active energy register,
these two values can be easily compared. The active and apparent
energies are calculated more accurately because of this precise
timing control. At the end of an energy calibration cycle, the
CYCEND flag in the interrupt status register is set. If the
CYCEND mask bit in the interrupt mask register is enabled, the
IRQ output also will go active low. Thus, the IRQ line can also
be used to signal the end of a calibration.
The line apparent energy accumulation uses the same signal path
as the apparent energy accumulation. The LSB size of these two
registers is equivalent.
48
23
LVAENERGY[23:0]
0
LVAENERGY REGISTER IS
UPDATED EVERY LINECYC
ZERO CROSSINGS WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
0
ADE7763