LTC4253IGN Linear Technology, LTC4253IGN Datasheet - Page 18

• Manufacturer Part Number: LTC4253IGN
• Description: IC HOT SWAP CONTRLR -48V 16-SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4253IGN

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 11.2 V ~ 14.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Family Name: LTC4253
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC4253/LTC4253A
applicaTions inForMaTion
POWER GOOD SEQUENCING
After the initial TIMER cycle, GATE ramps up to turn on
the external MOSFET which in turn pulls DRAIN low.
When GATE is within 2.8V of V
V
ing active low. This starts off a 5µA pull-up on the SQTIMER
pin which ramps up until it reaches the 4V threshold then
pulls low. When the SQTIMER pin floats, this delay t
about 300µs. Connecting an external capacitor C
SQTIMER to V
PWRGD2 asserts when EN2 goes high and PWRGD1 has
asserted for more than one t
cessfully pulls low, SQTIMER ramps up on another delay
cycle. PWRGD3 asserts when EN2 and EN3 go high and
PWRGD2 has asserted for more than one t
All three PWRGD signals are reset in UVLO, in UV condi-
tion, if RESET is high or when C
addition, PWRGD2 is reset by EN2 going low. PWRGD3 is
reset by EN2 or EN3 going low. An overvoltage condition
has no effect on the PWRGD flags. A 50µA current pulls
each PWRGD pin high when reset. As power modules
signal common are different from PWRGD, optoisolation
is recommended. These three pins can sink an optodiode
current. Figure 17 shows an NPN configuration for the
PWRGD interface. A limiting base resistor should be used
for each NPN and the module enable input should have
protection from negative bias current.
SOFT-START
Soft-start is effective in limiting the inrush current during
GATE start-up. Unduly long soft-start intervals can exceed
the MOSFET’s SOA duration if powering-up into an active
load. When the SS pin floats, an internal current source
ramps SS from 0V to 2.2V in about 300µs (0V to 1.4V in
about 200µs for the LTC4253A). Connecting an external
capacitor, C
approximate an RC response of:
18
DRNL
t
SQT
, the power good sequence starts with PWRGD1 pull-
=
4V • C
SS
5µA
, from SS to ground modifies the ramp to
EE
SQ
modifies the delay to:
IN
SQT
and DRAIN is lower than
. When PWRGD2 suc-
T
charges up to 4V. In
SQT
.
SQ
SQT
from
(5)
is
An internal resistor divider (95k/5k for the LTC4253 and
47.5k/2.5k for the LTC4253A) scales V
times to give the analog current limit threshold:
This allows the inrush current to be limited to V
The offset voltage, V
discharged and the ACL amplifier is in current limit mode
before GATE start-up. SS is discharged low during UVLO
at V
circuit breaker fault or the RESET pin going high.
GATE
GATE is pulled low to V
tions: in UVLO, when RESET pulls high, in an undervoltage
condition, in an overvoltage condition, during the initial
timing cycle or a latched circuit breaker fault. When GATE
turns on, a 50µA current source charges the MOSFET gate
and any associated external capacitance. V
gate drive to no more than 14.5V.
Gate-drain capacitance (C
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at V
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating C
capacitor C
for the analog current limit loop.
GATE has two comparators: the GATE low comparator looks
for <0.5V threshold prior to initial timing; the GATE high
comparator looks for <2.8V relative to V
with DRAIN low comparator, sets PWRGD1 output during
GATE start-up.
V
V
IN
SS
ACL
, UV, OV, during the initial timing cycle, a latched
(t) ≈ V
(t) =
C
is adequate. C
SS
V
SS
20




(t)
1− e
GD
OS
– V
. Instead, a smaller value (≥10nF)
EE
R
(10mV), ensures C
OS
SS
– t
under any of the following condi-
C
SS
C
GD




also provides compensation
) feedthrough at the first
SS
IN
SS
(t) down by 20
and, together
is sufficiently
IN
ACL
limits the
(t)/R
425353afd
(6)
(7)
IN
S
.