LTC4253IGN Linear Technology, LTC4253IGN Datasheet - Page 25

• Manufacturer Part Number: LTC4253IGN
• Description: IC HOT SWAP CONTRLR -48V 16-SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4253IGN

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 11.2 V ~ 14.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Family Name: LTC4253
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

applicaTions inForMaTion
V
checks for OV < V
0.8V, GATE < V
TIMER < V
starts and the TIMER capacitor is charged by a 5µA current
source pull-up. At time point 3, TIMER reaches the V
threshold and the initial timing cycle terminates. The TIMER
capacitor is quickly discharged. At time point 4, the V
threshold is reached and the conditions of GATE < V
SENSE < V
the GATE start-up cycle begins. SS ramps up as dictated
by R
limit amplifier until SS crosses 20 • V
GATE, 50µA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches SS control level and the analog current limit loop
activates. Between time points 6 and 8, the GATE voltage
is servoed and the SENSE voltage is regulated at V
and soft-start limits the slew rate of the load current. If the
SENSE voltage (V
at time point 7, the circuit breaker TIMER activates. The
TIMER capacitor, C
current pull-up. As the load capacitor nears full charge,
load current begins to decline. At point 8, the load cur-
rent falls and the SENSE voltage drops below V
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below V
discharge current source (cool-off). When GATE ramps
past V
starting off the PWRGD sequence. PWRGD2 pulls low at
time point C when EN2 is high and PWRGD1 is low for
more than one t
when EN2 and EN3 is high and PWRGD2 is low for more
than one t
voltage as determined by V
UVHI
SS
(V
GATEH
• C
UV
CB
SQT
TMRL
for the LTC4253A). In addition, the internal logic
CB
and the fault TIMER ends, followed by a 5µA
SS
threshold at time point A, PWRGD1 pulls low,
. At time point B, GATE reaches its maximum
; GATE is held low by the analog current
and SS < 20 • V
. When all conditions are met, initial timing
GATEL
SQT
SENSE
OVHI
T
. PWRGD3 pulls low at time point D
, SENSE < V
is charged by a (200µA + 8 • I
(V
– V
OV
EE
IN
for the LTC4253A), RESET <
) reaches the V
.
OS
must be satisfied before
CB
, SS < 20 • V
OS
. Upon releasing
CB
threshold
OS
ACL
GATEL
ACL
TMRH
TMRL
DRN
and
(t).
(t)
)
,
Undervoltage Timing
In Figure 10 when the UV pin drops below V
V
LTC4253A shut down with TIMER, SS and GATE pulled
low. If current has been flowing, the SENSE pin voltage
decreases to zero as GATE collapses. When UV recovers
and clears V
an initial time cycle begins followed by a start-up cycle.
V
V
timing behavior as the UV pin timing except it looks at
V
In an undervoltage lockout condition, both UV and OV
comparators are held off. When V
lockout, the UV and OV comparators are enabled.
Overvoltage Timing
During normal operation, if the OV pin exceeds V
(V
ure 11, the TIMER and PWRGD status are unaffected; SS
and GATE pull down; load disconnects. At time point 2,
OV recovers and drops below the V
for the LTC4253A) threshold; GATE start-up begins. If
the overvoltage glitch is long enough to deplete the load
capacitor, time points 4 through 7 may occur.
Circuit Breaker Timing
In Figure 12a, the TIMER capacitor charges at 200µA if
the SENSE pin exceeds V
the SENSE pin returns below V
the V
Figure 12b, when TIMER exceeds V
down immediately and the chip shuts down. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach V
and the chip shuts down. During chip shutdown, the
LTC4253/LTC4253A latch TIMER high with a 5µA pull-up
current source.
UVHST
IN
IN
IN
OV
undervoltage lockout comparator, UVLO has a similar
< (V
Undervoltage Lockout Timing
for the LTC4253A) as shown at time point 1 of Fig-
TMRH
for the LTC4253A) at time point 1, the LTC4253/
LKO
– V
threshold, TIMER is discharged by 5µA. In
UVHI
LKH
LTC4253/LTC4253A
(V
) to shut down and V
UV
TMRH
for the LTC4253A) at time point 2,
CB
followed by GATE pull down
but V
CB
before TIMER reaches
DRN
IN
OVLO
exits undervoltage
TMRH
is less than 5V. If
IN
> V
(V
, GATE pulls
OV
UVLO
LKO
– V
to start.
25
(V
425353afd
OVHST
UV
OVHI
–