AMIS30624C6245RG ON Semiconductor, AMIS30624C6245RG Datasheet - Page 38

• Manufacturer Part Number: AMIS30624C6245RG
• Description: IC STEPPER DVR I2C 800MA 32-NQFP
• Manufacturer: ON Semiconductor
• Type: I2C Micro Stepping Motor Driverr

Specifications of AMIS30624C6245RG

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: 800mA
• Voltage - Supply: 8 V ~ 29 V
• Operating Temperature: -40°C ~ 165°C
• Mounting Type: Surface Mount
• Package / Case: 32-VSQFP
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 8 V to 29 V
• Supply Current: 800 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 766-1002-2

AMIS-30624
2) If the microcontroller wants to receive information from motordriver_2:
Even in this case the master generates the timing and terminates the transfer.
Generation of the signals on the I
transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow slave device
holding-down the clock line.
15.3 General Characteristics
Both SDA and SCK are bi-directional lines connected to a positive supply voltage via a pull-up resistor (see Figure 24). When the bus is
free both lines are HIGH. The output stages of the devices connected to the bus must have an open drain to perform the wired-AND
function. Data on the I
dependent on the maximum bus capacitance limit (See C
15.4 Bit Transfer
The levels for logic ‘0’ (LOW) and ‘1’ (HIGH) are not fixed in the I
the levels are specified in Table 5. One clock pulse is generated for each data bit transferred.
• Microcontroller (master) addresses motordriver_2 (slave)
• Microcontroller (master-receiver) receives data from motordriver_2 (slave-transmitter)
• Microcontroller terminates the transfer
Serial Data Line
Serial Clock Line
Clock IN
Clock OUT
AMIS-30624
2
C-bus can be transferred up to 400kbits/s in fast mode. The number of interfaces connected to the bus is
SCK
2
C-bus is always the responsibility of the master device. It generates its own clock signal when
2
Data IN
Data OUT
Figure 24: Connection of a Device to the I
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SDA
B
1
in Table 6) and the available number of addresses.
2
C standard but dependent on the used VDD level. Using AMIS-30624,
Clock IN
Clock OUT
MASTER
SCL
2
C-bus
Data IN
Data OUT
SDA
+5 V
R
PC20060925.7
p
R
p