A3979SLPTR-T Allegro Microsystems Inc, A3979SLPTR-T Datasheet - Page 7

• Manufacturer Part Number: A3979SLPTR-T
• Description: IC DRIVER MICROSTEPPING 28-TSSOP
• Manufacturer: Allegro Microsystems Inc

Specifications of A3979SLPTR-T

• Applications: Stepper Motor Driver
• Number Of Outputs: 1
• Current - Output: ±2.5A
• Voltage - Load: 8 V ~ 35 V
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Motor Type: DMOS
• No. Of Outputs: 2
• Output Current: 2.5A
• Output Voltage: 35V
• Supply Voltage Range: 3V To 5.5V
• Driver Case Style: TSSOP
• No. Of Pins: 28
• Operating Temperature Range: -20°C To +85°C
• Operating Current: 8mA
• Operating Temperature Classification: Commercial
• Package Type: TSSOP EP
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 620-1148-2; A3979SLPTR-T

A3979
Device Operation.
stepping motor driver with a built-in translator for easy
operation with minimal control lines. It is designed to
operate bipolar stepper motors in full-, half-, quarter-, and
sixteenth-step modes. The currents in each of the two output
full-bridges (all of the N-channel MOSFETs) are regulated
with fixed off-time PMW (pulse width modulated) control
circuitry. At each step, the current for each full-bridge is
set by the value of its external current-sense resistor (R
or R
of its DAC (which in turn is controlled by the output of the
translator).
At power-on or reset, the translator sets the DACs and the
phase current polarity to the initial Home state (shown in
figures 2 through 5), and the current regulator to Mixed
decay mode for both phases. When a step command signal
occurs on the STEP input, the translator automatically
sequences the DACs to the next level and current polarity.
(See table 2 for the current-level sequence.) The microstep
resolution is set by the combined effect of inputs MS1 and
MS2, as shown in table 1.
While stepping is occurring, if the next output level of the
DACs is lower than the immediately preceeding output
level, then the decay mode (Fast, Slow, or Mixed) for the
active full bridge is set by the PFD input. If the next DAC
output level is higher than or equal to the preceeding level,
then the decay mode for that full bridge will be Slow decay.
This automatic current-decay selection improves microstep-
ping performance by reducing the distortion of the current
waveform due to back EMF of the motor.
RESET Input ( ¯ R ¯ ¯ E ¯ ¯ S ¯ ¯ E ¯ ¯ T ¯ ).
low) sets the translator to a predefined Home state (shown
in figures 2 through 5), and turns off all of the DMOS out-
puts. The HOME output goes low and all STEP inputs are
ignored until the ¯ R ¯ ¯ E ¯ ¯ S ¯ ¯ E ¯ ¯ T ¯ input is set to high.
Home Output
output indicator of the initial state of the translator. At
power-on, the translator is reset to the Home state (shown in
figures 2 through 5).
S2
), a reference voltage (V
(HOME)
The A3979 is a complete micro-
.
The HOME output is a logic
REF
The ¯ R ¯ ¯ E ¯ ¯ S ¯ ¯ E ¯ ¯ T ¯ input (active
), and the output voltage
DMOS Microstepping Driver with Translator
Functional Description
Functional Description
S1
Step Input
STEP input sequences the translator and advances the motor
one increment. The translator controls the input to the DACs
and the direction of current flow in each winding. The size
of the increment is determined by the combined state of
inputs MS1 and MS2 (see table 1).
Microstep Select
terminals MS1 and MS2 selects the microstepping format,
as shown in table 1. Any changes made to these inputs do not
take effect until the next rising edge of a step command signal
on the STEP input.
Direction Input
mines the direction of rotation of the motor. Any changes
made to this input does not take effect until the next rising
edge of a step command signal on the STEP input.
Internal PWM Current Control.
controlled by a fixed–off-time PWM current-control circuit
that limits the load current to a desired value, I
a diagonal pair of source and sink MOS outputs are enabled
and current flows through the motor winding and the current
sense resistor, R
DAC output voltage, the current-sense comparator resets the
PWM latch. The latch then turns off either the source MOS-
FETs (when in Slow decay mode) or the sink and source
MOSFETs (when in Fast or Mixed decay mode).
The maximum value of current limiting is set by the selec-
tion of R
ductance function approximated by:
The DAC output reduces the V
rent-sense comparator in precise steps (see table 2 for
% I
It is critical that the maximum rating (0.5 V) on either the
SENSE1 and SENSE2 pins is not exceeded. For full step-
ping, V
because the peak sense value is 0.707 × V
modes, V
TRIP
REF
max at each step).
S
REF
I
and the voltage at the V
TRIP
can be applied up to the maximum rating of V
should not exceed 4 V.
(STEP)
= (% I
Sx
I
. When the voltage across R
TRIP
(DIR). The state of the DIR input deter-
.
(MS1 and MS2). The input on
max = V
TRIP
A low-to-high transition on the
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
max/100) I
REF
REF
REF
output to the cur-
/8R
input with a transcon-
Each full bridge is
TRIP
S
REF
max
/ 8. In all other
Sx
TRIP
equals the
. Initially,
DD
7