MAX8555AEUB+ Maxim Integrated Products, MAX8555AEUB+ Datasheet - Page 14

• Manufacturer Part Number: MAX8555AEUB+
• Description: IC CNTRLR MOSFET ORING 10-UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX8555AEUB+

• Applications: Telecom Supplies, Rectifiers
• Fet Type: N-Channel
• Number Of Outputs: 1
• Internal Switch(s): No
• Delay Time - Off: 100ns
• Voltage - Supply: 8 V ~ 13.25 V
• Current - Supply: 2mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - On: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Use a resistor-divider from the input supply to GND with
the center tap connected to UVP to set the undervoltage
threshold. Use a 10kΩ resistor from UVP to GND (R4 in
Figure 4) and calculate R3 as follows:
where V
V
UVP to VL to disable the undervoltage-protection feature.
For a single-supply application, use a resistor-divider
from the output bus to GND with the center tap con-
nected to OVP to set the overvoltage threshold. Use a
10kΩ resistor from OVP to GND (R6 in Figure 4) and
calculate R5 as follows:
where V
is the OVP reference threshold (0.5V typ). Connect OVP
to GND to disable the overvoltage-protection feature.
For (n + 1) applications, the required circuit values are:
where the resistors are as shown in Figure 2.
The MAX8555/MAX8555A drive N-channel MOSFETs.
The most important specification of the MOSFETs is
R
MOSFET, V
the MOSFET’s on-resistance, R
MAX8555A monitor V
determine the state of the monitored power supply.
Selecting a MOSFET with a low R
current to flow through the MOSFETs before the
MAX8555/MAX8555A detect reverse-current (I
and forward-current (I
Low-Cost, High-Reliability, 0.5V to 3.3V ORing
MOSFET Controllers
14
UVP
DS(ON)
______________________________________________________________________________________
is the UVP reference threshold (0.4V typ). Connect
OV
UV
. As load current flows through the external
is the desired overvoltage threshold and V
DS
is the desired undervoltage trip point and
is generated from source to drain due to
R
R
R A
R B
R
R
2
2
Set the UVP Fault Threshold
Set the OVP Fault Threshold
6 1
5
5
3
= Ω
=
=
DS
=
= ×
FORWARD
R
=
k
R
R
2
6
47
6
4
of the MOSFETs at all times to
×
k



R






Ω
V
V
5
V
V
V
V
OVP
UVP
OVP
OV
OV
UV
) conditions.
MOSFET Selection
DS(ON)
−
−
−
1
1
1
DS(ON)









. The MAX8555/
allows more
REVERSE
OVP
)
Two MOSFETs must be used for overvoltage protec-
tion. When using two external MOSFETs, the monitored
voltage equation becomes:
A single MOSFET can be used if the overvoltage-protec-
tion function is not needed. Connect CS+ to the source of
the MOSFET and CS- to the drain of the MOSFET.
The charge-pump output current is proportional to both
oscillator frequency and V
nal load of approximately 6MΩ. The GATE current for a
given V
It is important to keep all traces as short as possible
and to maximize the high-current trace dimensions to
reduce the effect of undesirable parasitic inductance.
The MOSFET dissipates a fair amount of heat due to
the high currents involved, especially during an over-
current condition. To dissipate the heat generated by
the MOSFET, make the power traces very wide with a
large amount of copper area and place the MAX8555
as close as possible to the drain of the external MOS-
FET. A more efficient way to achieve good power dissi-
pation on a surface-mount package is to lay out two
copper pads directly under the MOSFET package on
both sides of the board. Use enlarged copper mount-
ing pads on the top side of the board. Use a ground
plane to minimize impedance and inductance. In addi-
tion to the usual high-power considerations, here are
three tips to prevent false faults:
1) Kelvin connect CS+ and CS- to the external
2) Bypass V
3) Make the traces connected to UVP and OVP as
Refer to the MAX8555/MAX8555A evaluation kit for an
example of good PC board layout.
I
GATE
V
DSTOTAL
MOSFET and route the two traces in parallel, as
close as possible, back to the IC.
bypass CS+ and CS- with a 1000pF capacitor to
ground.
short as possible.
≈
VL



 
24 12
and R
.
= R
DD
×
TIMER
DS(ON)1
with a 0.01µF capacitor to ground and




(
V
L
3 4
−
Calculating GATE Current
is calculated as:
.
0 8
. )
x I
VL
LOAD




. There is also a small inter-
×




1
Layout Guidelines
−
Using Two MOSFETs
+ R
Using One MOSFET




R
12 500
DS(ON)2
TIMER
,








x I
−
0 4
LOAD
.



 
µ
A