STW4810CRAT/LF ST-Ericsson Inc, STW4810CRAT/LF Datasheet
STW4810CRAT/LF
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STW4810CRAT/LF Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - STMicroelectronics ...
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Features ■ 2 Step-down converters – 1.5V with 15 steps at 600mA – 1.8V at 600mA for general purpose usage ■ 3 Low-drop output regulators for different uses – PLL analog supplies: 1.05V, 1.2V, 1.3V 1.8V - 10mA ...
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Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STw4810 5 Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 Absolute maximum rating . . ...
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List of tables List of tables Table 1. STw4810 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STw4810 Table 49. CMOS input/output static characteristics VMMC level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 50. ...
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List of figures List of figures Figure 1. Typical mobile multimedia system . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STw4810 1 Overview The STw4810 power management device has the following features: ● Power management module – 1 Step-down converter for processor core (1 to 1.5 V with 15 steps at 600 mA) – 1 Step-down converter (1 ...
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Functional block diagram 2 Functional block diagram Figure 2. STw4810 block diagram VBAT_DIG Internal oscillator VMINUS_DIG MASTER_CLK clock switching CLK32K_IN and CLK32K control GPO1 GPO2 Control USBINTn registers TCXO_EN REQUEST_MC PON VDDOK General PORn control PWREN SW_RESETn I2C SDA interface ...
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STw4810 3 Ball information 3.1 Ball connections Table 1. STw4810 ball connections VLX_VIO_ VMINUS_ VMEM A CLK32K_IN VIO_VMEM REQUEST_ VMINUS_ B “Reserved” MC VIO_VMEM IT_WAKE_ VMINUS_ C TCXO_EN UP DIG MASTER_ D VBAT_DIG “reserved” CLK DATAOUT DATAOUT ...
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Ball information Table 2. STw4810 balls function Ball Ball name General supplies D1 VBAT_DIG C3 VMINUS_DIG C6 VBAT_ANA B5 VMINUS_ANA F9 VBAT_USB J9 VMINUS_USB A9 VREF_18 Control balls C8 PON K4 SW_RESETn J2 VDDOK J3 PORn H6 PWREN C1 TCXO_EN ...
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STw4810 Table 2. STw4810 balls function (continued) Ball Ball name Regulator balls A4 VBAT_VIO_VMEM B4 A2 VMINUS_VIO_VMEM B3 A3 VLX_VIO_VMEM C4 A5 VIO_VMEM D9 VBAT_VCORE D10 B10 VMINUS_VCORE C9 C10 VLX_VCORE D8 A10 VCORE C7 VBAT_VPLL_ANA A7 VANA A8 VPLL ...
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Ball information Table 2. STw4810 balls function (continued) Ball Ball name J10 CN G10 VBUS F10 VUSB G9 USBSCL H9 USBSDA H8 USBINTn SD MMC balls G3 MCCMDDIR K2 MCDAT0DIR K9 MCDAT2DIR H4 MCDAT31DIR G2 MCCLK H5 MCFBCLK H1 MCCMD ...
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STw4810 Table 2. STw4810 balls function (continued) Ball Ball name F1 E3 DATAOUT[3: VBAT_MMC K5 VMMC Other balls J5 GPO1 K6 GPO2 B9 “Reserved” “Reserved” K10 Ball type DIO(VMMC) Bidirectional data[3:1] ...
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Functional description 4 Functional description 4.1 Introduction The STw4810 integrates all the power supplies for a multimedia processor as well as memories and peripherals: ● Two switched mode power supply regulators: one for the multimedia processor core, one for multimedia ...
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STw4810 REQUEST_MC ball. STw4810 remains in internal oscillator mode until it receives the external clock signal on MASTER_CLK ball. EXT_CLK: When MASTER_CLK is detected, the STw4810 uses this clock as reference and switches off its internal oscillator to save quiescent. ...
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Functional description Figure 3. Start-up timing OFF VBAT PON ball 300µs PDN__OSC 7.77ms (9.46ms wc) PDN_regulators VDDOK ball (*) CLK32K_IN ball PORn ball PWREN ball Internal_OSC MASTER_CLK ball TCXO_EN ball REQUEST_MC ball Voutput(s) ball CLK32K ball Delays are worst case ...
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STw4810 Figure 4. Switching POWER to sleep timing HPM PWREN Sleep regulators VDDOK PDN_regulators CLK32K PDN_intOSC int_OSC_detect REQUEST_MC Internal_OSC MASTER_CLK Registers reset In the event of a hardware reset coming from the modem, PON ball set to “0”, all registers ...
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Functional description 4.2.2 POWER OFF / VDDOK ● In case of VDDOK falling edge due to under voltage on VCORE or VIO_VMEM detected, or ‘it_twarn’ bit set to “1” ( (PORn low during a minimum time of 312.5 µs) and ...
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STw4810 4.2.4 I2C Interface The device supports two I2C bus interfaces. One main interface (SDA,SCL) controls power management and all programmable functions, the second interface (USBSDA, USBSCL) is dedicated to USB control. STw4810 allows to work with only the main ...
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Functional description Table 3. Device AdrID6 AdrID5 AdrID4 Table 4. Register address b7 b6 RegADR7 RegADR6 RegADR5 Table 5. Register data b7 b6 DATA7 DATA6 DATA5 I2C interface modes Figure 7. Control interface: I2C format DEVICE ADDRESS ...
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STw4810 4.2.5 Control registers Control registers have the following functions: – Select level of regulation for multimedia processor supply – Control the USB interface – Control the SD/MMC/SDIO interface – Control the state machine Table 6. Register general information Address ...
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Functional description Table 8. Power control register Register Addr. Power control 1Fh Register Addr. Power control 1 Eh Registers controlled by I2C USB bus The registers described in this chapter are controlled through the USB serial I2C interface, USBSCL and ...
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STw4810 Table 10. Vendor ID and Product ID: Read only Name Vendor ID Vendor ID Product ID USB control register 1 Table 11. USB control register 1 (address = 04h set and 05h clearh) Register Bit name Type Bits Name ...
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Functional description USB control register 2 Table 12. USB control register 2 (Address = 06h set and 07h clearh) Register Bit name Type Bits Name 7 vbus_chrg 6 vbus_dischrg 5 vbus_drv 4 id_gnd 3 dn_pulldown 2 dp_pulldown 1 dn_pullup 0 ...
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STw4810 USB interrupt source register Table 13. USB Interrupt source register (address = 08h) Register Bit name Type Bits Name 7 cr_int 6 bdis_acon 5 id_float 4 dn_hi 3 id_gnd_forced 2 dp_hi 1 sess_vld vbus_vld 0 USB latch register Table ...
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Functional description USB interrupt mask false register Table 15. USB interrupt mask false register (address = 0Ch and 0Dh) Register Bit name Default Type USB interrupt mask false register bits enable transition from true to false. USB interrupt mask true ...
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STw4810 Registers controlled by main I2C bus I²C controlled registers are controlled through the main serial I2C interface, SCL and SDA balls. SD MMC control register Table 18. SD MMC control register (11h) Register Bit name Type 1. These bits ...
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Functional description Power control register at address 1Eh Table 19. Power control register - General information (Address = 1Eh) Register Bit name Type Bits Name reg address 3 [7:5] bits data din/ [4:1] dout 4 bits EN 0 Power control ...
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STw4810 Power control register at address 05h Table 22. Power control register at address 05h Address 1Fh Not used Bits Name [4:1] vcore_sel [3: ...
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Functional description Power control register at address 06h Table 23. Power control register at address 06h Address 1Fh Not used Bits Name vpll_sel[1: 06h and 07h address [3:2] vaux_sel[1:0] 1 usb_i2c_ctrl Power control register ...
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STw4810 Power control register at address 08h Table 25. Power control register at address 08h Address 1Fh Not used Bits Name 4 en_clock_squarer 3 en_monitoring 2 en_vana Power control register at address 09h Table 26. Power ...
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Functional description Power control register at address 0Ah Table 27. Power control register at address 0Ah Address 1Fh Not used Bits Name 4 vaux_force_sleep vio_vmem_force_ 2 sleep 1 vcore_force_sleep Twarning register Table 28. Twarning register (Address ...
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STw4810 4.2.6 IT generation STw4810 has three interrupt balls: IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is plugged this interrupt is activated to wake up the host or the modem, depends of application (active ...
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Functional description 4.3 Power management module STw4810 includes several regulators that supply the multimedia processor and its peripherals. All regulators can work in different modes depending on the processor needs. When the STw4810 is in ‘low current mode’”, the output ...
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STw4810 4.3.2 VCORE regulator: DC/DC step-down regulator This regulator drives the core of the multimedia processor. VCORE is a DC/DC step-down regulator that generates the regulated power supply with very high efficiency. The 15 voltage levels enable dynamic voltage and ...
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Functional description Fast switching from low current to normal mode. The regulator is in ‘low current mode’ when multimedia processor is in sleep mode. PWREN signal indicates that the multimedia processor is about to switch to run mode. VDDOK signal ...
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STw4810 4.3.6 VAUX This LDO is dedicated either to the multimedia processor input/output signals or to the auxiliary devices. Power supply values are 1.5 V,1.8 V, 2.5 V, 2.8 V with 150 mA full load and 0 sleep ...
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Functional description 4.3.9 Thermal shut-down A thermal sensor is used to monitor the die temperature. ● As soon as the die temperature exceeds the thermal warning rising threshold, VDDOK ball goes to “0” and ‘it_warn’ bit is set to “1” ...
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STw4810 4.4 USB OTG module This transceiver complies with the USB specification: ● Universal Serial Bus specification revision 2.0 ● ‘On the Go’ supplement to the USB specification revision 1.0-a ● Car kit interface specification (see: OTG transceiver specification revision ...
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Functional description 4.4.1 Block diagram Figure 12. USB OTG transceiver block diagram VBAT_DIG vbus_vld VMINUS_DIG sess_vld dn_hi Interrupt dp_hi Control bdis_acon USB_INTn Register id_gnd_forced id_float cr_int usb_en usb_i2c_ctrl vbus_drv bdis_acon_en dn_pullup dp_pullup USBSCL Control dn_pulldown Registers dp_pulldown USBSDA id_gnd vbus_chrg ...
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STw4810 VBUS monitoring These comparators monitor the VBUS voltage. They detect the current status of the VBUS line: ● VBUS > 4.4 V means VBUS_VALID ● 2 V<VBUS<4.4 V means SESSION_VALID ● VBUS<0.8 V means SESSION_END These three bits generate ...
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Functional description Data transmission The transceiver transmits USB data in the following conditions for USB control register 1 uart_en=0; oe_int_en=0 Table 31. Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0 Inputs USB mode (DAT_SE0) USBVP ...
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STw4810 The transceiver receives USB data in the following conditions: uart_en = 0 (USB control register 1); oe_int_en = 1 Table 33. Data receiver via USB control register 1 USB mode (dat_se0) 1 (DAT_SE0 mode) 1 (DAT_SE0 mode) 1 (DAT_SE0 ...
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Functional description VBUS monitoring and control The monitoring is made of three comparators that determine if the VBUS voltage valid level for operation: ● VBUS valid: It corresponds to the minimum level on VBUS. Any voltage on ...
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STw4810 The two bits of USB control register dp_pullup and dn_pullup ( connect/disconnect pull-up resistors. Session Request Protocol (SRP) To save power, the OTG supplement allows an A-device to leave the VBUS turned off when the bus is not being ...
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Functional description ● Host Negotiation Protocol (HNP) At the start of a session, the A-device has the role of host as default. During a session, the host role can be transferred back and forth between the A-device and the B-device ...
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STw4810 4.4.3 USB enable control STw4810 OFF In this state, the overall system is able to detect USB connection through IT_WAKE_UP ball and with VBUS session valid comparator and ID detection ON. IT_WAKE_UP is activated (low level) in either of ...
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Functional description 4.5 SD/MMC/SDIO module This block provides the power supply (1 and signal shifting functions required to connect any of the following peripherals to the multimedia processor: – SD card – MMC cards, ...
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STw4810 5 Electrical and timing characteristics Otherwise specified parameters are defined for T = 25°C. / VBAT = 3.6 V 5.1 Absolute maximum rating Table 34. STw4810 absolute maximum ratings Symbol Maximum power supply Ta Maximum operating ambient temperature V ...
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Electrical and timing characteristics 5.3.1 Operating conditions Table 36. Operating conditions (Temp range: -30 to +85 °C) Symbol Description V Power supply BAT I QSLEEP Quiescent Current I QSTDBY 5.3.2 VREF18 Table 37. VREF18 Symbol Description V Supply voltage BAT ...
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STw4810 5.3.3 VCORE DC/DC step-down converter Table 38. VCORE DC/DC step-down converter Symbol Description VCORE regulator in normal mode (SLEEP = ‘0’) / Otherwise specified; VCORE = 1 Input power supply Battery voltage BAT Output voltage V RIPPLE ...
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Electrical and timing characteristics Table 38. VCORE DC/DC step-down converter (continued) Symbol Description VCORE regulator in sleep mode (SLEEP= ‘1’) V Input power supply Battery voltage BAT VCORE output V RIPPLE voltage ripple L Line regulation IR L Load regulation ...
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STw4810 Table 39. VIO_VMEM DC/DC step-down converter (continued) Symbol Description VIO_VMEM regulator in sleep mode (SLEEP=’1’) V Input power supply Battery voltage BAT V Output ripple RIPPLE L Line regulation IR L Load regulation DR I Output current OUT P ...
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Electrical and timing characteristics 5.3.5 LDO regulators VPLL Table 40. LDO regulators - VPLL Symbol Description VPLL regulator in normal mode / otherwise specified, VPLL = 1 Input power supply Battery voltage BAT V Output voltage OUT I ...
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STw4810 VANA Table 41. LDO regulators - VANA Symbol Description VANA regulator in normal mode V Input power supply Battery voltage BAT V Output voltage OUT I Output current OUT Short-circuit I SHORT limitation I Quiescent current Q Power-down I ...
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Electrical and timing characteristics Table 42. LDO regulators - VAUX (continued) Symbol Description Power supply (1) PSRR rejection L Line regulation IR (1) L Load regulation DR Transient line L IRT regulation Transient load L DRT regulation t Settling time ...
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STw4810 5.3.6 Power supply monitoring This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM drops below the threshold, the multimedia processor is reset. Table 43. Power supply monitoring Symbol Description Threshold (1) T Threshold VCORE HCORE ...
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Electrical and timing characteristics 5.4.2 CMOS input/output dynamic characteristics: I2C interface Table 45. CMOS input/output dynamic characteristics: I²C interface Symbol I²C interface ( Figure 8 Fscl Clock frequency thigh Clock pulse width high tlow Clock pulse width low tr SDA, ...
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STw4810 5.4.3 CMOS input/output static characteristics: VIO level USB and control I/Os Table 46. VIO level: USB and control I/Os Symbol Description SW_RESETn, VDDOK, PORN, PWREN, TCXO_EN, REQUEST_MC, CLK32K, CLK32K_IN, USBOEN, USBVP, USBVM, USBRCV, USBINTn, MASTER_CLK Low level input (1) ...
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Electrical and timing characteristics MMC Interface Table 47. VIO level: MMC interface Symbol Description MMC interface: MCCLK, MCFBCLK, MCCMDDIR, MCCMD, MCDATA2DIR, MCDAT2, MCDATA0DIR, MCDAT0, MCDAT31DIR, MCDAT3, MCDAT1 Low level input ( voltage High level input V IH voltage ...
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STw4810 5.4.4 CMOS input/output static characteristics: VBAT level Table 48. CMOS input/output static characteristics: VBAT level Symbol Description IT_WAKE_UP, PON, GPO1, GPO2 Low level input V IL voltage High level input V IH voltage Low level input I IL current ...
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Electrical and timing characteristics 5.4.5 CMOS input/output static characteristics: VMMC level Table 49. CMOS input/output static characteristics VMMC level Symbol Description DATAOUT0, DATAOUT1, DATAOUT2, DATAOUT3, CMDOUT, LATCHCLK, CLKOUT Low level input V IL voltage High level input V IH voltage ...
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STw4810 5.5 USB OTG transceiver Table 50. USB OTG transceiver Symbol Description UART mode t Rise time R t Fall time F Drive propagation t PLH delay low => high Drive propagation t PHL delay high => low USB full ...
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Electrical and timing characteristics Table 50. USB OTG transceiver (continued) Symbol Description VBUS R A_BUS_IN T A_VBUS_ RISE Data line pull-down resistance R PD_DPDN Data line pull-up resistance R PU_DP R PU_DN Pull-down on VBUS R VBUS_PD Pull-up on VBUS ...
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STw4810 Table 50. USB OTG transceiver (continued) Symbol Description Charge pump V Input power supply BAT V Output voltage BUS t Settling time S IQ Quiescent current Amplitude output ripple VRipple on VBUS I Output current OUT Eff Efficiency VUSB ...
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Electrical and timing characteristics 5.6 SD/MMC card interface Table 51. SD/MMC card interface Symbol Description VMMC regulator specifications (PDN_VMMC = 1) V Input voltage BAT V Output voltage OUT I Output current OUT Short circuit I SHORT current limitation IQ ...
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STw4810 Table 51. SD/MMC card interface (continued) Symbol Description Propagation time T PHC from Host to card Propagation time T PCH from card to host Clock /data skew T time from host to SHC card Clock /data skew T time ...
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Electrical and timing characteristics Figure 14. Propagation and clock/data skew times 2 ns MCCLK 90% MCCMD MCDATA[3:0] 10% MCFBCLK T PHC CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK 2 ns CLKOUT 90% CMDOUT DATAOUT[3:0] 10% LATCHCLK T PCH MCCLK MCCMD MCDATA[3:0] MCFBCLK 68/78 ...
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STw4810 6 Application information 6.1 Components list Table 52. Components list Typical Name value C1 22µ 10µF In the complete system application, C5 the sum of the capacitors connected on each STw4810 ball must never be C6 ...
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Application information Table 54. Other ST components Name EMIF02 EMIF06 70/78 Order code EMIF02USB05 USB ESD/EMI Protection EMIF06-HMC01F2 MMC Interface ESD/EMI Protection STw4810 Function ...
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STw4810 6.2 Application schematics Figure 15. STw4810 application schematics (*) C13 VBAT_DIG VMINUS_DIG PON CLK32Kin MASTER_CLK IT_WAKE_UP REQUEST_MC TCXO_EN B9 D3 PWREN VDDOK PORn CLK32K SW_RESETn SCL SDA USBVP USBOEn USBVM USBRCV USBINTn USBSCL USBSDA MCCLK MCFBCLK MCCMDDIR MCCMD MCDAT0DIR ...
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Package mechanical data 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and ...
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STw4810 Figure 16. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing Note: The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package ...
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Package mechanical data 7.2 VFBGA 84 balls See Figure 17: VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing Table 56. VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch Drawing dimensions (mm ...
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STw4810 Figure 17. VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing Note: The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral ...
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... Ordering information 8 Ordering information Table 57. Order codes Part number STw4810CHDR/LF STw4810CHDT/LF STw4810CRAE/LF STw4810CRAT/LF 76/78 Package TFBGA84 1 0.5 mm pitch TFBGA84 1 0.5 mm pitch VFBGA 84 - 4.6x 4 0.4 mm pitch VFBGA 84 - 4.6x 4 0.4 mm pitch STw4810 Packing Tray Tape and reel Tray Tape and reel ...
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STw4810 9 Revision history Table 58. Document revision history Date 24-Jan-2006 07-Feb-2006 09-Feb-2006 10-Mar-2006 25-Jul-2006 30-Nov-2006 15-Mar-2007 23-Apr-2007 08-Jun-2007 03-Sep-2007 Revision 1 Initial release. Modified document title. Reviewed list of applications on cover page. Replaced APE with multimedia processor. 2 ...
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...