LTC2938CDE#TRPBF Linear Technology, LTC2938CDE#TRPBF Datasheet - Page 14

• Manufacturer Part Number: LTC2938CDE#TRPBF
• Description: IC FOUR PWR SUPPLY MONITOR 12DFN
• Manufacturer: Linear Technology

Specifications of LTC2938CDE#TRPBF

• Applications: Four Power Supply Monitor
• Voltage - Supply: 1 V ~ 5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 12-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Input: -

LTC2938/LTC2939
APPLICATIONS INFORMATION
After RST returns high, the microprocessor can poll the
state of the WDO pin to determine if the reset was caused
by an undervoltage condition or by a watchdog timeout.
WDO high means that the reset was caused by undervolt-
age since this condition also resets the WDO latch (and
the watchdog timer). If the WDO pin is low, the system
reset was caused by watchdog timeout. The microproces-
sor can then change the state of WDI to clear the WDO
latch. If the microprocessor fails to do so, the LTC2938/
LTC2939 will alternate between t
and RST will be pulled low for t
timeout. WDO remains low until the microprocessor fl ips
the state of WDI.
Some microprocessors force their I/O pins into high
impedance during reset which in turn, fl oats the WDI
14
5V
3.3V
2.5V
1.8V
12V
1.2V
124k 1%
Figure 5. 6-Supply Monitor, 12V (ADJ), 5V, 3.3V, 2.5V, 1.8V, 1.2V (ADJ)
RST
2150k 1%
RST
after every watchdog
100k
1%
0.1μF
and t
100k
1%
WD
with Watchdog Enabled
timeout
R1
59k
1%
R2
40.2k
1%
0.1μF
V1
V2
V3
V4
V5
V6
V
V
REF
PG
GND CRT
pin. This affects the response of the LTC2938/LTC2939.
When the WDI pin is fl oated, the watchdog timer is reset
and C
unchanged. Putting WDI in high impedance does not affect
t
high impedence to a high or low state, the watchdog timer
starts a complete t
low-to-high transition at WDI clears WDO if it was previ-
ously latched low.
The RST and WDO pins should not be tied together to
generate the master reset signal since a watchdog timeout
forces RST low together with WDO and the master reset
signal will remain low indefi nitely.
RST
LTC2939
. Once RST goes high again, and WDI is driven from
WT
C
47nF
RT
is discharged towards ground but WDO remains
293839 F05
WDO
CWT
WDI
RST
C
47nF
WT
WD
MICROPROCESSOR
t
t
RST
WD
timeout period. A high-to-low or
= 940ms
= 94ms
293839ff