LT3150CGN#PBF Linear Technology, LT3150CGN#PBF Datasheet - Page 16

• Manufacturer Part Number: LT3150CGN#PBF
• Description: IC CTRLR REG VLDO FET 16-SSOP
• Manufacturer: Linear Technology
• Type: Positive Adjustabler

Specifications of LT3150CGN#PBF

• Number Of Outputs: 1
• Voltage - Output: 2.5 ~ 18.4 V
• Current - Supply: 12mA
• Voltage - Input: 1.5 ~ 10 V, 10 ~ 20 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SSOP
• Primary Input Voltage: 10V
• Dropout Voltage Vdo: 130mV
• No. Of Pins: 16
• Output Current: 10A
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 1 - Unlimited
• Output Voltage Adjustable Min, Vout: 1.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
LT3150
higher unity gain bandwidth crossover frequency, f
must be set to a value that provides adequate phase and
gain margin and this criteria limits the shelf gain value. If
higher shelf gain is required for a given application, then
increase output capacitance.
In both output capacitor cases, the location of the second
pole, P2, is set by the MOSFET’s transconductance, g
and the value of the output capacitor, C
current sets the transconductance of the MOSFET. P2
moves as a function of load current and consequently, so
does the unity-gain crossover frequency, f
5 depict this behavior. At very low output currents, P2’s
location moves to a very low frequency. Therefore, set Z1
at a low enough frequency to provide adequate phase boost.
A temptation is to set Z1’s value equal to P2’s value at
minimum output load current. The bode plot then exhibits
a single pole response at minimum output current. How-
ever, this either makes the “shelf gain” and f
stability or it makes the small signal settling time very long.
Set Z1 above the minimum value for P2 so that at small
output load currents, the second pole P2 occurs and then
Z1 provides phase boost prior to crossing unity gain.
At the highest load current levels, several poles and zeros
exist just beyond the unity-gain crossover frequency.
Sometimes, the gain peaks back above unity and a high
frequency, low level oscillation appears. A high frequency
16
P1 = 1/(2 • • R
Figure 4. Typical Bode Plot for
Low ESR Ceramic Output Capacitors
AVOL = g
I
f
LOAD(MIN)
X
= g
MANY HIGH ORDER POLES AND
U
FREQUENCY (Hz)
m1
m1
Z1 = 1/(2 • • R1 • C1)
ZEROS PAST UNITY-GAIN f
• R1 •
O
• R
• C1)
O
U
• (V
V
V
REF
OUT
REF
P2 = g
•
/V
AV1 = g
2 • • C
OUT
g
m
m
(Q1)
(Q1)/(2 • • C
)
W
m1
O
I
LOAD(MAX)
• R1 • (V
X
O
3150 F04
OF LOAD CURRENT
. The output load
P2 IS A FUNCTION
X
O
. Figures 4 and
REF
)
X
/V
too high for
OUT
U
)
m
(Q1),
X
. f
X
pole is necessary to roll off the response. In the case of
ceramic output capacitors, capacitor C2 in Figure 4 sets
this pole in combination with R1. In the case of electrolytic
or tantalum output capacitors, some small ceramic ca-
pacitors in parallel with the main output capacitors usually
provide the desired response.
Finally, look for very high frequency gate oscillations in the
range of 2MHz to 10MHz. Small MOSFETs with low gate
capacitance are most susceptible to this issue. This oscil-
lation is typically caused by the MOSFET’s “effective” gate
capacitance and the MOSFET’s parasitic source induc-
tance resonating. The MOSFET’s source inductance is the
sum of the device’s bond wire plus package lead induc-
tance and the PCB trace inductance between the MOSFET’s
source and the actual output capacitors. Although the
MOSFET’s internal inductance is fixed, proper PCB layout
techniques minimize the external inductance. Minimize
the distance between the MOSFET’s source and the output
decoupling capacitors and run wide planes if possible.
Connect the top of the feedback divider at the point closest
to the actual load rather than the MOSFET source. If high
frequency oscillations persist, a small value resistor in the
range of 1 to 50 in series with the gate of the MOSFET
typically eliminates this ringing. The inclusion of a gate
resistor may permit the high frequency pole discussed in
the preceding paragraph to be eliminated or fine tuned.
Figure 5. Typical Bode Plot for Tantalum
or Electrolytic Output Capacitors
P1 = 1/(2 • • R
AVOL = g
I
LOAD(MIN)
MANY HIGH ORDER POLES AND
FREQUENCY (Hz)
m1
f
Z1 = 1/(2 • • ESR • C
X
ZEROS PAST UNITY-GAIN f
O
=
• R
• C1)
2 • • C1
O
g
• (V
m1
REF
P2 = g
/V
AV1 = AVOL • (P1/P2)
OUT
m
(Q1)/(2 • • C
= (g
)
O
)
m1
I
LOAD(MAX)
• C
X
3150 F05
OF LOAD CURRENT
O
P2 IS A FUNCTION
)/(g
O
m
)
(Q1) • C1)
3150f