LTC3722EGN-2 Linear Technology, LTC3722EGN-2 Datasheet - Page 14

• Manufacturer Part Number: LTC3722EGN-2
• Description: IC CTRLR PWM VOLTAGE-MODE 24SSOP
• Manufacturer: Linear Technology

Specifications of LTC3722EGN-2

• Pwm Type: Voltage Mode, Full Bridge
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 98.5%
• Voltage - Supply: 3.8 V ~ 10.3 V
• Buck: No
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: Yes
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-SSOP
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC3722-1/LTC3722-2
operaTion
network to implement. If there is not enough energy to
fully commutate the bridge leg to a ZVS condition, the
LTC3722-1/LTC3722-2 automatically overrides the Di-
rectSense circuitry and forces a transition. The override
or default delay time is programmed with a resistor from
DPRG to V
Adaptive Mode
The LTC3722-1/LTC3722-2 are configured for adaptive
delay sensing with three pins, ADLY, PDLY and SBUS.
ADLY and PDLY sense the active and passive delay legs
respectively via a voltage divider network, as shown in
Figure 2.
The threshold voltage on PDLY and ADLY for both the ris-
ing and falling transitions is set by the voltage on SBUS.
A buffered version of this voltage is used as the threshold
level for the internal DirectSense circuitry. At nominal V
the voltage on SBUS is set to 1.5V by an external voltage
divider between V
proportional to V
circuitry uses this characteristic to zero voltage switch
all of the external power MOSFETs, independent of input
voltage.
ADLY and PDLY are connected through voltage dividers to
the active and passive bridge legs respectively. The lower
resistor in the divider is set to 1k. The upper resistor in
the divider is selected for the desired positive transition
trip threshold.
To set up the ADLY and PDLY resistors, first determine at
what drain to source voltage to turn-on the MOSFETs. Finite

SBUS
PDLY
REF
R2
R1
.
IN
Figure 2. Adaptive Mode
R3
1k
IN
. The LTC3722-1/LTC3722-2 DirectSense
R5
and GND, making this voltage directly
V
IN
A
B
R
CS
C
D
R6
372212 F02
R4
1k
ADLY
IN
,
delays exist between the time at which the LTC3722-1/
LTC3722-2 controller output transitions, to the time at
which the power MOSFET switches on due to MOSFET
turn-on delay and external driver circuit delay. Ideally, we
want the power MOSFET to switch at the instant there
is zero volts across it. By setting a threshold voltage for
ADLY and PDLY corresponding to several volts across the
MOSFET, the LTC3722-1/LTC3722-2 can anticipate a zero
voltage VDS and signal the external driver and switch to
turn-on. The amount of anticipation can be tailored for
any application by modifying the upper divider resistor(s).
The LTC3722-1/LTC3722-2 DirectSense circuitry sources
a trimmed current out of PDLY and ADLY (proportional
to SBUS) after a low to high level transition occurs. This
provides hysteresis and noise immunity for the PDLY and
ADLY circuitry, and sets the high to low threshold on ADLY or
PDLY to nearly the same level as the low to high threshold,
thereby making the upper and lower MOSFET VDS switch
points virtually identical, independent of V
Example: V
1. Set up SBUS: 1.5V is desired on SBUS with V
2. Set up ADLY and PDLY: 7V of anticipation is desired
Set divider current to 100µA.
An optional small capacitor (0.001µF) can be added
across R1 to decouple noise from this input.
in this circuit to account for the delays of the external
MOSFET driver and gate drive components.
R3, R4 = 1k, sets a nominal 1.5mA in the divider chain
at the threshold.
use (2) equal 13k segments.
R
R
R R
1
2
5 6
,
=
=
100
48
1 5
.
=
100
IN
V
µA
V
−
= 48V nominal (36V to 72V)
(
48
µA
1 5
=
.
V
15
V
−
1 5
k
.
=
7
V
mA
465
−
1 5
k
.
V
)
=
26 3
. ,
IN
k
.
IN
= 48V.
372212fa