UC2843BDR2G ON Semiconductor, UC2843BDR2G Datasheet - Page 10

• Manufacturer Part Number: UC2843BDR2G
• Description: IC CTRLR CURRENT MODE HP 14-SOIC
• Manufacturer: ON Semiconductor

Specifications of UC2843BDR2G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 96%
• Voltage - Supply: 11 V ~ 25 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Frequency-max: 275kHz
• Duty Cycle (max): 96 %
• Output Voltage: 4.95 V to 5.05 V
• Output Current: 1000 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 500 KHz
• Operating Supply Voltage: 30 V
• Maximum Operating Temperature: + 85 C
• Fall Time: 50 ns
• Minimum Operating Temperature: - 25 C
• Rise Time: 50 ns
• Synchronous Pin: No
• Topology: Boost, Flyback, Forward
• Number Of Pwm Outputs: 1
• On/off Pin: No
• Adjustable Output: No
• Switching Freq: 500KHz
• Operating Supply Voltage (max): 30V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Undervoltage Lockout
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (V
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The V
upper and lower thresholds are 16 V/10 V for the UCX842B,
and 8.4 V/7.6 V for the UCX843B. The V
upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX842B makes
it ideally suited in off−line converter applications where
efficient bootstrap startup techniques are required
(Figure 34). The UCX843B is intended for lower voltage
DC−to−DC converter applications. A 36 V Zener is
connected as a shunt regulator from V
purpose is to protect the IC from excessive voltage that can
occur during system startup. The minimum operating
voltage (V
UCX843B.
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull−down resistor.
pins for V
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the I
clamp level. The separate V
designer added flexibility in tailoring the drive voltage
independent of V
to this input when driving power MOSFETs in systems
where V
power and control ground connections in a current−sensing
power MOSFET application.
Reference
tolerance at T
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short−
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
Two undervoltage lockout comparators have been
These devices contain a single totem pole output stage that
The SOIC−14 surface mount package provides separate
The 5.0 V bandgap reference is trimmed to ±1.0%
CC
CC
C
is greater than 20 V. Figure 26 shows proper
) for the UCX842B is 11 V and 8.2 V for the
(output supply) and Power Ground. Proper
J
= 25°C on the UC284XB, and ±2.0% on the
CC
CC
. A Zener clamp is typically connected
) and the reference output (V
C
supply input allows the
CC
CC
ref
to ground. Its
comparator
comparator
ref
pk(max)
http://onsemi.com
) are
10
Design Considerations
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to V
and V
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise−generating components.
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
shows the phenomenon graphically. At t
conduction begins, causing the inductor current to rise at a
slope of m
divided by the inductance. At t
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m
condition can be shown if a perturbation is added to the
control voltage, resulting in a small DI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turn−on (t
by DI + DI m
(t
is multiplied by m
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the DI perturbation will decrease to zero
on succeeding cycles. This compensating ramp (m
have a slope equal to or slightly greater than m
stability. With m
inductor current follows the control voltage, yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
3
Do not attempt to construct the converter on
Current mode converters can exhibit subharmonic
) decreases to (DI + DI m
ref
may be required depending upon circuit layout.
1
. This slope is a function of the input voltage
2
, until the next oscillator cycle. The unstable
2
/m
1
2
. The minimum current at the next cycle
/m
2
/2 slope compensation, the average
1
2
on each succeeding cycle, alternately
/m
1
2
/m
is greater than 1, the converter
1
) (m
1
, the Current Sense Input
2
/m
1
). This perturbation
2
) is increased
0
, switch
CC
3
2
) must
/2 for
, V
C
,