UC2843BDR2G ON Semiconductor, UC2843BDR2G Datasheet - Page 8

• Manufacturer Part Number: UC2843BDR2G
• Description: IC CTRLR CURRENT MODE HP 14-SOIC
• Manufacturer: ON Semiconductor

Specifications of UC2843BDR2G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 96%
• Voltage - Supply: 11 V ~ 25 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Frequency-max: 275kHz
• Duty Cycle (max): 96 %
• Output Voltage: 4.95 V to 5.05 V
• Output Current: 1000 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 500 KHz
• Operating Supply Voltage: 30 V
• Maximum Operating Temperature: + 85 C
• Fall Time: 50 ns
• Minimum Operating Temperature: - 25 C
• Rise Time: 50 ns
• Synchronous Pin: No
• Topology: Boost, Flyback, Forward
• Number Of Pwm Outputs: 1
• On/off Pin: No
• Adjustable Output: No
• Switching Freq: 500KHz
• Operating Supply Voltage (max): 30V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

fixed frequency, current mode controllers. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost−effective
solution
representative block diagram is shown in Figure 18.
Oscillator
selected for the timing components R
is charged from the 5.0 V reference through resistor R
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of C
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. Figure 2 shows R
and Figure 3, Output Deadtime versus Frequency, both for
given values of C
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency.
The oscillator thresholds are temperature compensated to
within ±6% at 50 kHz. Also because of industry trends
moving the UC384X into higher and higher frequency
applications, the UC384XB is guaranteed to within ±10% at
250 kHz. These internal circuit refinements minimize
variations of oscillator frequency and maximum output duty
cycle. The results are shown in Figures 4 and 5.
to frequency−lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 21. For reliable locking, the
free−running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi−unit
synchronization is shown in Figure 22. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved.
Error Amplifier
inverting input and output is provided. It features a typical
DC voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 8). The
non−inverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is −2.0 mA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
loop compensation (Figure 32). The output voltage is offset
by two diode drops (≈1.4 V) and divided by three before it
connects to the non−inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
the Output (Pin 6) when pin 1 is at its lowest state (V
The UC3842B, UC3843B series are high performance,
The oscillator frequency is programmed by the values
In many noise−sensitive applications it may be desirable
A fully compensated Error Amplifier with access to the
The Error Amp Output (Pin 1) is provided for external
with
T
. Note that many values of R
minimal
T
external
versus Oscillator Frequency
T
and C
components.
T
, the oscillator
T
. Capacitor C
OPERATING DESCRIPTION
T
and C
http://onsemi.com
T
OL
T
will
to
A
).
T
8
This occurs when the power supply is operating and the load
is removed, or at the beginning of a soft−start interval
(Figures 24, 25). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (V
comparator’s 1.0 V clamp level:
Current Sense Comparator and PWM Latch
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the peak inductor current on a
cycle−by−cycle basis. The Current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
ground−referenced sense resistor R
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared to a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
pin 1 where:
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of R
level. A simple method to adjust this voltage is shown in
Figure 23. The two external diodes are used to compensate
the internal diodes, yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the I
voltage.
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 27).
The UC3842B, UC3843B operate as a current mode
Abnormal operating conditions occur when the power
When designing a high power switching regulator it
A narrow spike on the leading edge of the current
R
f(min)
≈
I
pk
3.0 (1.0 V) + 1.4 V
I
pk(max)
=
V
0.5 mA
(Pin 1)
=
3 R
− 1.4 V
1.0 V
S
R
S
S
= 8800 W
in series with the
S
OH
to a reasonable
pk(max)
) to reach the
clamp