LTC1753CSW Linear Technology, LTC1753CSW Datasheet - Page 6

• Manufacturer Part Number: LTC1753CSW
• Description: IC SW REG CNTRLR PENT III 20SOIC
• Manufacturer: Linear Technology

Specifications of LTC1753CSW

• Applications: Controller, Intel Pentium® III
• Voltage - Input: 5V
• Number Of Outputs: 1
• Voltage - Output: 1.3 ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1753
TYPICAL PERFOR A CE CHARACTERISTICS
PI FU CTIO S
G2 (Pin 1): Gate Drive for the Lower N-Channel MOSFET,
Q2. This output will swing from PV
be low when G1 is high or when the output is disabled. To
prevent undershoot during a soft-start cycle, G2 is held
low until G1 first goes high.
PV
connected to a potential of at least V
normal applications, connect PV
or generate PV
GND (Pin 3): Power Ground. GND should be connected to
a low impedance ground plane in close proximity to the
source of Q2.
SGND (Pin 4): Signal Ground. SGND is connected to the
low power internal circuitry and should be connected to
the negative terminal of the output capacitor where it
returns to the ground plane. GND and SGND should be
shorted directly at the LTC1753.
V
power circuity. V
drain of Q1 if they share the same supply. A 10 F bypass
capacitor is recommended from this pin to SGND.
SENSE (Pin 6): Output Voltage Pin. Connect to the positive
terminal of the output capacitor. There is an internal 108k
resistor connected from this pin to SGND. SENSE is a very
sensitive pin; for optimum performance, connect an exter-
nal 1 F capacitor from this pin to SGND. By connecting a
small external resistor between the output capacitor and
6
CC
CC
U
(Pin 5): Power Supply. Power for the internal low
(Pin 2): Power Supply for G1 and G2. PV
U
20mV/DIV
10V/DIV
CC
V
OUT
G1
CC
using a simple charge pump.
Expanded View of Undershoot
Illustrates 100% Duty Cycle
Operation, V
U
should be wired separately from the
W
OUT
CC
5 s/DIV
U
CC
= 2.8V
to a 12V power supply
to GND. It will always
IN
+ V
GS(ON)Q1
CC
1753 G18
must be
. For
the SENSE pin, the initial output voltage can be raised
slightly. Since the internal divider has a nominal imped-
ance of 108k , a 1100
nominal output voltage by 1%. If an external resistor is
used, the value of the 1 F capacitor on the SENSE pin must
be greatly reduced or loop phase margin will suffer. Set a
time constant for the RC combination of approximately
0.1 s. So, for example, with a 1100
C = 90pF. Use a standard 100pF capacitor. In addition, LTC
recommends that the 1 F capacitor be connected from the
top of the additional external resistor directly to SGND.
I
by the voltage drop across an external resistor connected
between the drain of Q1 and I
pull-down at I
I
switching node between the source of Q1 and the drain of
Q2. If I
will go into current limit. The current limit circuit can be
disabled by floating I
SS (Pin 9): Soft-Start. Connect to an external capacitor to
implement a soft-start function. During moderate over-
load conditions, the soft-start capacitor will be discharged
slowly in order to reduce the duty cycle. In hard current
limit, the soft-start capacitor will be forced low immedi-
ately and the LTC1753 will rerun a complete soft-start
cycle. C
current through Q1 will not exceed the current limit value.
MAX
FB
(Pin 8): Current Limit Sense Pin. Connect to the
20mV/DIV
(Pin 7): Current Limit Threshold. Current limit is set
10V/DIV
FB
SS
V
OUT
G1
drops below I
must be selected such that during power-up the
Expanded View of Overshoot
Illustrates 0% Duty Cycle
Operation, V
MAX
.
MAX
OUT
MAX
5 s/DIV
and shorting I
= 2.8V
series resistor will raise the
MAX
when G1 is on, the LTC1753
. There is a 190 A internal
1753 G19
FB
to V
resistor, set
CC
.
1753fa