ADP3209JCPZ-RL ON Semiconductor, ADP3209JCPZ-RL Datasheet - Page 17

• Manufacturer Part Number: ADP3209JCPZ-RL
• Description: IC CTRLR BUCK 5BIT GMCH 32LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3209JCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 1.25 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Output Voltage: 0.4 V to 1.25 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADP3209JCPZ-RLTR

remains connected to the DAC. The ST buffer input recognizes the
almost instantaneous VID voltage change and tries to track it.
However, tracking is not instantaneous because the slew rate of the
buffer is limited by the source and sink current capabilities (7.5 µA
and 2.5 µA, respectively) of the ST output. Therefore, the V
voltage slew rate is controlled. When the transient period is
complete, the reference input of the voltage amplifier reverts to the
VID DAC output to improve accuracy.
Charging/discharging the external capacitor on the ST pin programs
the voltage slew rate of the ST pin and consequently of the V
output.
CURRENT LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3209 has an adjustable current limit set by the R
resistor. This resistor is connected from the CLIM pin to GND,
and the CLIM pin outputs a 10 μA current. The voltage created
by 10 μA through R
and connected in series with CSCOMP to form a current limit
threshold. The current sense amplifier sets an output voltage
between CSREF and CSCOMP that is proportional to the output
current. When the difference in voltage between CSREF and
CSCOMP is greater than the current limit threshold, there is a
current overload.
Normally, the ADP3209 operates in RPM mode. During a
current overload, the ADP3209 switches to PWM mode.
With low impedance loads, the ADP3209 operates in a constant
current mode to ensure that the external MOSFETs and inductor
function properly and to protect the GPU. With a low constant
impedance load, the output voltage decreases to supply only the
set current limit. If the output voltage drops below the power-
good limit, the PWRGD signal transitions. After the PWRGD
single transitions, the SS capacitor begins to discharge with a
2 µA internal constant current sink. When the SS capacitor has
discharged voltage from 2.9 V to 1.65 V, the ADP3209 latches
off. The current limit latch-off delay time is therefore set by the
SS pin capacitance. Figure 23 shows how the ADP3209 reacts to
a current overload.
3
4
1
2
CURRENT LIMIT
APPLIED
CLIM
Figure 23. Current Overload
OUTPUT VOLTAGE 1V/DIV
is divided by 10 and then level shifted
PWRGD 2V/DIV
SWITCH NODE 10V/DIV
1ms/DIV
SS PIN 2V/DIV
LATCHED
OFF
Rev. 2 | Page 17 of 32 | www.onsemi.com
CCGFX
CCGFX
CLIM
The latch-off function can be reset either by removing and
reapplying VCC or by briefly pulling the EN pin low. To disable
the current limit latch-off function, an external resistor pulls the
SS pin to the VCC voltage to override the 2 µA sink current.
This pull-up prevents the SS capacitor from discharging to the
1.65 V latch-off threshold.
During startup, when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot extend below ground. This
secondary current limit clamp controls the minimum internal
COMP voltage to the PWM comparators to 1.5 V. This limits
the voltage drop across the low-side MOSFETs through the
current balance circuitry.
The ADP3209 operates in RPM mode. With higher loads, the
ADP3209 operates in continuous conduction mode (CCM),
and the upper and lower MOSFETs run synchronously and in
complementary phase. See Figure 24 for the typical waveforms
of the ADP3209 running in CCM with a 7 A load current.
With lighter loads, the ADP3209 enters discontinuous con-
duction mode (DCM). Figure 25 shows a typical single-phase
buck with one upper FET, one lower FET, an output inductor,
an output capacitor, and a load resistor. Figure 26 shows the
path of the inductor current with the upper FET on and the
lower FET off. In Figure 27 the high-side FET is off and the low-
side FET is on. In CCM, if one FET is on, its complementary FET
must be off; however, in DCM, both high- and low-side FETs are
off and no current flows into the inductor (see Figure 28). Figure
29 shows the inductor current and switch node voltage in
DCM.
In DCM with a light load, the ADP3209 monitors the switch
node voltage to determine when to turn off the low-side FET.
Figure 30 shows a typical waveform in DCM with a 1 A load
current. Between t
current flows through the source drain of the low-side FET and
creates a voltage drop across the FET with a slightly negative
switch node. As the inductor current ramps down to 0 A, the
3
4
2
1
Figure 24. Single-Phase Waveforms in CCM
1
SWITCH NODE 5V/DIV
LOW-SIDE GATE DRIVE 5V/DIV
and t
INDUCTOR CURRENT 5A/DIV
OUTPUT VOLTAGE 20mV/DIV
2
, the inductor current ramps down. The
1ms/DIV