LT3689EMSE-5#PBF Linear Technology, LT3689EMSE-5#PBF Datasheet - Page 23

• Manufacturer Part Number: LT3689EMSE-5#PBF
• Description: IC BUCK 5V 0.7A 16MSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT3689EMSE-5#PBF

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 5V
• Current - Output: 700mA
• Frequency - Switching: 350kHz ~ 2.2MHz
• Voltage - Input: 3.6 ~ 36 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-MSOP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

APPLICATIONS INFORMATION
Example: switching should not start until the input is above
4.40V, and is to stop if the input falls below 4V.
Keep the connection from the resistor to the EN/UVLO
pin short and make sure the interplane or surface capaci-
tance to switching nodes is minimized. If high resistor
values are used, the EN/UVLO pin should be bypassed with
a 1nF capacitor to prevent coupling problems from the
switch node.
Output Voltage Monitoring
The LT3689 provides power supply monitoring for micro-
processor-based systems. The features include power-on
reset (POR) and watchdog timing.
A precise internal voltage reference and glitch immune
precision POR comparator circuit monitor the LT3689
output voltage. The switcher’s output voltage must be
above 90% of programmed value for RST not to be asserted
(refer to the Timing Diagram). The LT3689 will assert RST
during power-up, power-down and brownout conditions.
Once the output voltage rises above the RST threshold,
the adjustable reset timer is started and RST is released
after the reset timeout period. On power-down, once the
output voltage drops below RST threshold, RST is held
at a logic low. The reset timer is adjustable using external
capacitors. The RST pin has a weak pull-up to the OUT pin.
The POR comparator is designed to be robust against FB
pin noise, which could potentially false trigger the RST pin.
The POR comparator lowpass filters the first stage of the
comparator. This filter integrates the output of the compara-
tor before asserting the RST. The benefit of adding this filter
is that any transients at the buck regulator’s output must
be of sufficient magnitude and duration before it triggers
a logic change in the output (see the Typical Transient vs
POR Comparator Overdrive in the Typical Performance
R3 =
R4 =
V
H
= 4.40V,V
4.40V − 4V
4.40V −1.26V
4µA
95.3k
1.26V
L
= 4V
− 4k = 95.3k
– 4µA
= 43.2k
(Nearest 1% Resistor)
Characteristics section). This prevents spurious resets
caused by output voltage transients such as load steps
or short brownout conditions without sacrificing the DC
reset threshold accuracy.
Watchdog
The LT3689 includes an adjustable watchdog timer that
monitors a µP’s activity. If a code execution error occurs
in a µP , the watchdog will detect this error and will set the
WDO low. This signal can be used to interrupt a routine
or to reset a microprocessor.
The watchdog is operated either in timeout or window
mode. In timeout mode, the microprocessor needs to
toggle the WDI pin before the watchdog timer expires, to
keep the WDO pin high. If no WDI pulse (either positive or
negative) appears during the programmed timeout period,
then the circuitry will pull WDO low. During normal opera-
tion, the WDI input signal’s high to low, and low to high
transition periods should be set lower than the watchdog’s
programmed time to keep WDO inactive.
In window mode, the watchdog circuitry is triggered by
negative edges on the WDI pin. The window mode restricts
the WDI pin’s negative going pulses to appear inside a
programmed time window (see the Timing Diagram) to
prevent WDO from going low. If more than two pulses are
registered in the watchdog lower boundary period, the WDO
is forced to go low. The WDI edges are ignored while the
C
low to high transition on the WDO or RST pin. The WDO
also goes low if no negative edge is supplied to the WDI
pin in the watchdog upper boundary period. During a code
execution error, the microprocessor will output WDI pulses
that would be either too fast or too slow. This condition
will assert WDO and force the microprocessor to reset the
program. In window mode, the WDI signal frequency is
bounded by an upper and lower limit for normal operation.
The WDI input frequency period should be higher than the
t
high under normal conditions. The window mode’s t
and t
These times can be increased or decreased by adjusting
an external capacitor on the C
WDL
WDT
period, and lower than the t
WDU
capacitor charges from 0V to 200mV right after a
times have a fixed ratio of 31 between them.
LT3689/LT3689-5
WDT
WDU
pin.
period, to keep WDO
23
3689fd
WDL