LTC1266CS Linear Technology, LTC1266CS Datasheet - Page 13

• Manufacturer Part Number: LTC1266CS
• Description: IC REG CNTRLR N/PCH MOSFET16SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck), Step-Up (Boost)r

Specifications of LTC1266CS

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: Adjustable
• Current - Output: 50mA
• Frequency - Switching: 400kHz
• Voltage - Input: 3.5 ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
The divided down voltage at the “–” input to the comparator
is compared to an internal 1.25V reference. This reference
is separate from the 1.265V reference used by the voltage
comparator and current comparator for regulation and is
not disabled by the shutdown pin, therefore the low-battery
detection is operational even when the rest of the chip is
shut down. The comparator is functional down to an input
voltage of 2.5V. Thus, the output will provide a valid state
even when the rest of the chip does not have sufficient
voltage to operate. For best performance, the value of the
pull-up resistor should be high enough that the output is
pulled down to ground when sinking 200 A or less.
Suppressing Burst Mode Operation
Normally, enabling Burst Mode operation is desired due to
its superior efficiency at low load currents (see Figure 7).
However, in certain applications it may be desirable to
inhibit this feature. Some reasons for doing so are:
1. To eliminate audible noise from certain types of induc-
tors at light loads.
V
IN
Figure 5. Comparison of Dropout Performance
600
500
400
200
100
300
0
0
R2
R1
Figure 6. Low-Battery Comparator
V
OUT
P-CHANNEL
= 3.3V
TOPSIDE
1
U U
–
+
LOAD CURRENT
TOPSIDE N-CHANNEL
WITH POWER V
2
1.25V
REFERENCE
N-CHANNEL WITH
3
CHARGE PUMP
IN
LTC1266
W
= 12V
TOPSIDE
4
1266 F06
1266 F05
5
LB
U
OUT
2. If the load is never expected to drop low enough to
benefit from the efficiency advantages of Burst Mode
operation, the output capacitor ESR and minimum capaci-
tance requirements (which may falsely trigger Burst Mode
operation if not met) can be relaxed if Burst Mode opera-
tion is disabled.
3. If an auxiliary winding is used. Disabling Burst Mode
operation guarantees switching independent of the load
on the primary. This allows power to be taken from the
auxiliary winding independently.
4. Tighter load regulation (< 1%).
Burst Mode operation is disabled by applying a CMOS
logic high voltage (> 2.1V) to Pin 4. When it is disabled, the
voltage comparator limit is raised high enough so that it no
longer is involved in regulation; however it is still active
and is useful as a voltage clamp to keep the output from
overshooting.
Note that since the inductor current must reverse to
regulate the output at zero load when Burst Mode opera-
tion is disabled, the minimum inductance (L
during Inductor Core Selection is no longer applicable.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to I
series resistance of C
Figure 7. Effect of Disabling Burst Mode Operation on Efficiency
100
90
80
60
70
0.01
Burst Mode OPERATION
LTC1266-3.3/LTC1266-5
LOAD
OUT
LOAD CURRENT (A)
0.1
ENABLED
(ESR), where ESR is the effective
. I
Burst Mode OPERATION
INHIBITED
LOAD
also begins to charge or
1
1266 F07
OUT
LTC1266
5
MIN
shifts by an
) specified
13