IP2005APBF International Rectifier, IP2005APBF Datasheet - Page 14

• Manufacturer Part Number: IP2005APBF
• Description: IC PWR BLOCK SYNC BUCK 40A LGA
• Manufacturer: International Rectifier
• Series: iPOWIR™r
• Type: Step-Down (Buck)r

Specifications of IP2005APBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 5.5 V
• Current - Output: 40A
• Frequency - Switching: 250kHz ~ 1.5MHz
• Voltage - Input: 6.5 ~ 13.2 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: Power Block (LGA)
• Power - Output: 9.3W
• Package: LGA - 7.7 x 7.7
• Circuit: Power Stage
• Iout (a): 40
• Switch Freq (khz): 250 - 1500
• Input Range (v): 6.5 - 13.2
• Output Range (v): 0.8 - 5.5
• Ocp Otp Uvlo Pre-bias Soft Start And: UVLO (no OVP OCP OTP nor Soft Start)
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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PCB Layout Guidelines
The following guidelines are recommended to reduce the parasitic values and optimize
• All pads on the iP2005A footprint design need to be Solder-mask defined (see Figure 12).
• Place as many vias around the Power pads (V
• A minimum of six 10µF, X5R, 16V ceramic capacitors per iP2005A are needed for greater
• Placement of the ceramic input capacitors is critical to optimize switching performance. In
• Dedicate at least two layer to for P
• Duplicate the Power Nodes on multiple layers (refer to AN1029).
overall performance.
Also refer to International Rectifier application notes AN1028 and AN1029 for further
footprint design guidance.
optimal thermal performance.
than 30A operation. This will result in the lowest loss due to input capacitor ESR.
cases where there is a heatsink on the case of iP2005A, place all six ceramic capacitors
right underneath the iP2005A footprint (see Figure 13 Bottom Component Layer). In
cases where there is not heatsink, C1 and C6 on the bottom layer may be moved to the
C1x and C6x locations (respectively) on the top component layer (see Figure 13 Top
Component Layer). In both cases, C2 – C5 need to be placed right underneath the
iP2005A PCB footprint.
Figure 13 Top & Bottom Component and Via Placement (Topside, Transparent view down)
GND
only
2/8/2008
IN
, V
SW
, and P
GND
) for both electrical and
iP2005APbF
PD-60325
14