CS51033GD8G ON Semiconductor, CS51033GD8G Datasheet - Page 5

• Manufacturer Part Number: CS51033GD8G
• Description: IC CTRLR PFET BUCK FAST 8-SOIC
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of CS51033GD8G

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.5V
• Current - Output: 200mA
• Frequency - Switching: 200kHz
• Voltage - Input: 3.14 ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

V
Control Scheme
when to turn on the P−Ch FET. If V
reference voltage of 1.25 V during the oscillator’s charge
cycle, the P−Ch FET is turned on and remains on for the
duration of the charge time. The P−Ch FET gets turned off
and remains off during the oscillator’s discharge cycle time
with the maximum duty cycle to 80%. It requires 7.0 mV
typical, and 20 mV maximum ripple on the V
operate. This method of control does not require any loop
stability compensation.
Startup
feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.
V
P−Ch FET off. As V
capacitor (C
(CS) charges via internal current sources. C
by the current source I
combination described by:
P−Ch FET is off until V
flip−flop (F2) from being set. This allows the oscillator to
reach its operating frequency before enabling the drive
output. Soft−Start is obtained by clamping the V
comparator’s (A6) reference input to approximately 1/2 of
the voltage at the CS pin during startup, permitting the
GATE
V
V
C
The CS51033 monitors the output voltage to determine
The CS51033 has an externally programmable Soft−Start
At startup, the voltage on all pins is zero. As V
The internal Holdoff Comparator ensures that the external
CS
FB
voltage along with the internal resistor R
1.25 V
1.15 V
2.6 V
2.4 V
1.5 V
0 V
Figure 3. Voltage on Start Capacitor (V
OSC
THEORY OF OPERATION
) and the Soft−Start/Fault Timing capacitor
I CS + I T *
CC
C
and V
START
T
and CS gets charged by the I
START
CS
S1
> 0.7 V, preventing the GATE
C
continue to rise, the oscillator
55
I T
FB
)
falls below the internal
I T
During Startup, Normal and Fault Conditions
5
NORMAL OPERATION
OSC
S2
gets charged
G
CC
CIRCUIT DESCRIPTION
FB
keeps the
rises, the
T
S1
http://onsemi.com
source
pin to
GS
), the Gate (V
FB
CS51033
5
td1
control loop and the output voltage to slowly increase. Once
the CS pin charges above the Holdoff Comparator trip point
of 0.7 V, the low feedback to the V
GATE flip−flop during C
GATE flip−flop is set, V
P−Ch FET. When V
comparator (A4) sets the V
V completing the startup cycle.
Lossless Short Circuit Protection
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage ) reaches
2.5 V, the fault timing circuitry is enabled. During normal
operation the CS voltage is 2.6 V. During a short circuit or
a transient condition, the output voltage moves lower and the
voltage at V
of the fault comparator goes high and the CS51033 goes into
a fast discharge mode. The fault timing capacitor, CS,
discharges to 2.4 V. If the V
when the CS pin reaches 2.4 V, a valid fault condition has
been detected. The slow discharge comparator output goes
high and enables gate G5 which sets the slow discharge
flip−flop. The V
is turned off. The fault timing capacitor is slowly discharged
to 1.5 V. The CS51033 then enters a normal startup routine.
If the fault is still present when the fault timing capacitor
voltage reaches 2.5 V, the fast and slow discharge cycles
repeat as shown in Figure 3.
a fault condition is not detected, normal operation resumes
and CS charges back to 2.6 V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
The CS51033 has “lossless” short circuit protection since
If the V
S2
GATE
S3
t
), and in the Feedback Loop (V
FB
FAULT
FB
voltage is above 1.15 V when CS reaches 2.4 V
drops. If V
GATE
S3
FAULT
CS
flip−flop resets and the output switch
t
RESTART
exceeds 2.4 V, the CS charge sense
FB
GATE
S1
FB
OSC
FB
drops below 1.15 V, the output
comparator reference to 1.25
voltage is still below 1.15 V
’s charge cycle. Once the
goes low and turns on the
td2
FB
S2
Comparator sets the
S3
t
FAULT
FB
),
S3
2.5 V
0 V