MAX1844ETP+ Maxim Integrated Products, MAX1844ETP+ Datasheet - Page 14

• Manufacturer Part Number: MAX1844ETP+
• Description: IC CNTRLR STP DWN HS 20-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Step-Down (Buck)r

Specifications of MAX1844ETP+

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.8V, 2.5V, Adj
• Current - Output: 4A
• Frequency - Switching: 200kHz, 300kHz, 450kHz, 600kHz
• Voltage - Input: 2 ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TQFN Exposed Pad
• Power - Output: 727mW
• Output Voltage: 1 V to 5.5 V, 1.8 V, 2.5 V
• Output Current: 4000 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 600 KHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Synchronous Pin: No
• Topology: Buck
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm (Figure 4). If the magnitude of the
current-sense voltage at CS is above the current-limit
threshold, the PWM is not allowed to initiate a new cycle.
The actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple cur-
rent. Therefore, the exact current-limit characteristic and
maximum load capability are a function of the sense
resistance, inductor value, and battery voltage.
There is also a negative current limit that prevents exces-
sive reverse inductor currents when V
rent. The negative current-limit threshold is set to
approximately 120% of the positive current limit and
therefore tracks the positive current limit when ILIM is
adjusted.
The current-limit threshold is adjusted with an external
resistor-divider at ILIM. A 1µA (min) divider current is
recommended. The current-limit threshold adjustment
range is from 25mV to 300mV. In the adjustable mode,
the current-limit threshold voltage is precisely 1/10 the
voltage seen at ILIM. The threshold defaults to 100mV
when ILIM is connected to V
switchover to the 100mV default value is approximately
V
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signal seen by CS. Mount or place the IC
close to the low-side MOSFET and sense resistor with
short, direct traces, making a Kelvin sense connection to
the sense resistor.
In Figure 1, the Schottky diode (D1) provides a current
path parallel to the Q2/R
current sensing demands D1 to be off while Q2 con-
ducts. Avoid large current-sense voltages that, com-
bined with the voltages across Q2, would allow D1 to
conduct. If very large sense voltages are used, connect
D1 in parallel with Q2.
The DH and DL drivers are optimized for driving moder-
ate-sized high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook environment, where a large V
V
monitors the DL output and prevents the high-side FET
from turning on until DL is fully off. There must be a low-
resistance, low-inductance path from the DL driver to the
MOSFET gate for the adaptive dead-time circuit to work
High-Speed Step-Down Controller with
Accurate Current Limit for Notebook Computers
14
CC
OUT
- 1V.
______________________________________________________________________________________
differential exists. An adaptive dead-time circuit
MOSFET Gate Drivers (DH, DL)
Current-Limit Circuit (ILIM)
SENSE
CC
. The logic threshold for
current path. Accurate
OUT
is sinking cur-
BATT
-
properly; otherwise, the sense circuitry in the MAX1844
will interpret the MOSFET gate as “off” while there is
actually still charge left on the gate. Use very short, wide
traces measuring no more than 20 squares (50 to 100
mils wide if the MOSFET is 1 inch from the MAX1844).
The dead time at the other edge (DH turning off) is deter-
mined by a fixed 35ns (typ) internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.5Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time of
the inductor node, due to capacitive coupling from the
drain to the gate of the low-side synchronous-rectifier
MOSFET. However, for high-current applications, there
are still some combinations of high- and low-side FETs
that will cause excessive gate-drain coupling, which can
lead to efficiency-killing, EMI-producing shoot-through
currents. This is often remedied by adding a resistor in
series with BST, which increases the turn-on time of the
high-side FET without degrading the turn-off time
(Figure 5).
Power-on reset (POR) occurs when V
approximately 2V, resetting the fault latch and soft-start
counter, and preparing the PWM for operation. Until V
reaches 4.2V, V
inhibits switching. DL is held low if overvoltage protec-
tion is disabled, and held high if overvoltage protection is
enabled. See the Output Overvoltage Protection section.
When V
timer begins to ramp up the maximum allowed current
limit. The ramp occurs in five steps: 20%, 40%, 60%,
80%, and 100%; 100% current is available after 1.7ms
±50%.
Figure 5. Reducing the Switching-Node Rise Time
MAX1844
CC
rises above 4.2V, an internal digital soft-start
CC
undervoltage lockout (UVLO) circuitry
BST
DH
LX
POR, UVLO, and Soft-Start
5Ω
+5V
CC
V
IN
rises above
CC