IDT89HPES3T3ZBBC8

Manufacturer Part NumberIDT89HPES3T3ZBBC8
DescriptionIC PCI SW 3LANE 3PORT 144-CABGA
ManufacturerIDT, Integrated Device Technology Inc
IDT89HPES3T3ZBBC8 datasheets

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Specifications of IDT89HPES3T3ZBBC8

Lead Free Status / RoHS StatusContains lead / RoHS non-compliantOther names89HPES3T3ZBBC8
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®
Device Overview
The 89HPES3T3 is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream
ports.
Features
◆
High Performance PCI Express Switch
– Three 2.5Gbps PCI Express lanes
– Three switch ports
– x1 Upstream port
– Two x1 Downstream ports
– Low latency cut-through switch architecture
– Support for Max payload sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆
Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆
Legacy Support
– PCI compatible INTx emulation
– Bus locking
Block Diagram
Frame Buffer
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
(Port 0)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
© 2010 Integrated Device Technology, Inc.
3-Lane 3-Port
PCI Express® Switch
◆
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates three 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
◆
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
◆
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCI-
PM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
◆
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
3-Port Switch Core / 3 PCI Express Lanes
Port
Route Table
Arbitration
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
(Port 2)
Figure 1 Internal Block Diagram
1 of 31
89HPES3T3
Data Sheet
Scheduler
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
(Port 3)
October 8, 2010

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IDT89HPES3T3ZBBC8 Summary of contents

  • Page 1

    Device Overview The 89HPES3T3 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES3T3 is a 3-lane, 3-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI ...

  • Page 2

    IDT 89HPES3T3 Data Sheet ◆ Five General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Four pins have selectable alternate functions ...

  • Page 3

    IDT 89HPES3T3 Data Sheet General Purpose Input/Output The PES3T3 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output ...

  • Page 4

    IDT 89HPES3T3 Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[7] GPIO[9] Signal APWRDISN CCLKDS CCLKUS PERSTN Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin ...

  • Page 5

    IDT 89HPES3T3 Data Sheet Signal RSTHALT SWMODE[2:0] WAKEN Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description I Reset Halt. When this signal ...

  • Page 6

    IDT 89HPES3T3 Data Sheet Pin Characteristics Note: Some input pads of the PES3T3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if ...

  • Page 7

    IDT 89HPES3T3 Data Sheet Logic Diagram — PES3T3 Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 3 Master SMBus Interface System Pins PEREFCLKP PEREFCLKN PE0RP[0] PE0RN[0] ...

  • Page 8

    IDT 89HPES3T3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter PEREFCLK Refclk Input reference clock frequency range FREQ 1 Refclk Duty cycle of ...

  • Page 9

    IDT 89HPES3T3 Data Sheet Signal GPIO GPIO[9,7,2:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, ...

  • Page 10

    IDT 89HPES3T3 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express ...

  • Page 11

    IDT 89HPES3T3 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 12. Maximum power is measured under the following conditions: ...

  • Page 12

    IDT 89HPES3T3 Data Sheet Thermal Considerations — Option B Package This section describes thermal considerations for the PES3T3 (10mm relevant to the thermal performance of the PES3T3 switch. Symbol T J(max) T A(max) θ Effective Thermal Resistance, Junction-to-Ambient JA(effective) θ ...

  • Page 13

    IDT 89HPES3T3 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V ...

  • Page 14

    IDT 89HPES3T3 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN ...

  • Page 15

    IDT 89HPES3T3 Data Sheet — 144-BGA Signal Pinout for PES3T3 Option A Package The following table lists the pin numbers and signal names for the PES3T3 device. Pin Function Alt Pin A1 V C11 C12 DD ...

  • Page 16

    IDT 89HPES3T3 Data Sheet Pin Function Alt Pin M5 PE3TP00 Option A Package — Alternate Signal Functions Option A Package — Power Pins V Core C11 ...

  • Page 17

    IDT 89HPES3T3 Data Sheet Option A Package — Ground Pins V A1 A12 B11 B12 C10 C12 Option A Package — Signals Listed Alphabetically Signal Name APWRDISN CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 ...

  • Page 18

    IDT 89HPES3T3 Data Sheet Signal Name No Connection PE0RN00 PE0RP00 PE0TN00 PE0TP00 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 PEREFCLKN PEREFCLKP PERSTN RSTHALT SWMODE_0 SWMODE_1 SWMODE_2 WAKEN V CORE APE ...

  • Page 19

    IDT 89HPES3T3 Data Sheet Option A Package Pinout — Top View Core (Power I/O (Power ...

  • Page 20

    IDT 89HPES3T3 Data Sheet Option A Package Drawing — 144-Pin BC144/BCG144 October 8, 2010 ...

  • Page 21

    IDT 89HPES3T3 Data Sheet Option A Package Drawing — Page Two October 8, 2010 ...

  • Page 22

    IDT 89HPES3T3 Data Sheet Package B Package Pinout — 132-QFN Signal Pinout for PES3T3 The following table lists the pin numbers and signal names for the PES3T3 132-pin device. Pin Function Alt Pin A1 NC A34 A2 NC A35 A3 ...

  • Page 23

    IDT 89HPES3T3 Data Sheet Package B Alternate Signal Functions Package B Power Pins V Core A21 A34 A40 A41 A52 A68 B5 B8 B10 Pin GPIO A50 GPIO_00 A49 GPIO_01 A48 GPIO_02 A42 GPIO_07 A39 GPIO_09 ...

  • Page 24

    IDT 89HPES3T3 Data Sheet Package B Ground Pins V A9 A43 A46 Package B No Connection Pins B11 B13 B15 B18 Table 26 PES3T3 (10x10, 132-pin) Ground Pins A17 ...

  • Page 25

    IDT 89HPES3T3 Data Sheet Package B Pin Signals Listed Alphabetically Signal Name APWRDISN CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_07 GPIO_09 JTAG_TCK JTAG_TDI JTAG_TDO JTAG-TMS JTAG-TRST_N MSMBCLK MSMBDAT NC PE0RN00 PE0RP00 PE0TN00 PE0TP00 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 ...

  • Page 26

    IDT 89HPES3T3 Data Sheet Signal Name PERSTN RSTHALT SWMODE_0 SWMODE_1 SWMODE_2 WAKEN V CORE APE Table 28 89PES3T3 (10x10, 132-pin) Alphabetical Signal List (Part 2 of ...

  • Page 27

    IDT 89HPES3T3 Data Sheet Package B Pinout — Top View A72 A71 A70 A69 A1 B60 B59 A10 B9 A11 B10 A12 B11 A13 ...

  • Page 28

    IDT 89HPES3T3 Data Sheet Package B Package Drawing — 132-Pin NQ132/NQG132 October 8, 2010 ...

  • Page 29

    IDT 89HPES3T3 Data Sheet Package B Package Drawing — Page Two October 8, 2010 ...

  • Page 30

    IDT 89HPES3T3 Data Sheet Revision History March 31, 2008: Publication of final data sheet. June 4, 2008: For the 132-QFN package, changed pins A44 and A45 from GPIO to No Connect and changed pin B6 from V August 6, 2008: ...

  • Page 31

    IDT 89HPES3T3 Data Sheet Ordering Information A AAA NN Product Operating Device Family Family Voltage Valid Combinations Option A Package 89HPES3T3ZBBC 144-pin BC144 package, Commercial Temperature 89HPES3T3ZBBCG 144-pin Green BC144 package, Commercial Temperature 89HPES3T3ZBBCI 144-pin BC144 package, Industrial Temperature 89HPES3T3ZBBCGI ...

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