IDT89HPES5T5ZBBCG IDT, Integrated Device Technology Inc, IDT89HPES5T5ZBBCG Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES5T5ZBBCG
• Description: IC PCI SW 5LANE 5PORT 196-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES5T5ZBBCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES5T5ZBBCG

General Purpose Input/Output
be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate
functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.
All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89PES5T5 Data Sheet
The PES5T5 provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may
The following tables lists the functions of the pins provided on the PES5T5. Some of the functions listed may be multiplexed onto the same pin. The
PEREFCLKP
PEREFCLKN
REFCLKM
PE0RP[0]
PE0RN[0]
PE0TN[0]
PE2RP[0]
PE2RN[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TN[0]
PE4RP[0]
PE4RN[0]
PE4TN[0]
PE5RP[0]
PE5RN[0]
PE5TN[0]
PE0TP[0]
PE2TP[0]
PE3TP[0]
PE4TP[0]
PE5TP[0]
Signal
Type
O
O
O
O
O
I
I
I
I
I
I
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pair for port 0.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 0.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 4.
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pair for port 5.
PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 5.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
4 of 28
Name/Description
May 7, 2009