IDT77V500S25PF8 IDT, Integrated Device Technology Inc, IDT77V500S25PF8 Datasheet - Page 10

• Manufacturer Part Number: IDT77V500S25PF8
• Description: IC SW MEMORY 8X8 1.2BGPS 100TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V500S25PF8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V500S25PF8

Manager Commands
Manager Commands
Manager Commands
Manager Commands
Manager Bus Read Timing Waveform
Manager Bus Read Timing Waveform
Manager Bus Read Timing Waveform
Manager Bus Read Timing Waveform
by the state of the MD/C pin.
Manager Bus Write Timing Waveform
Manager Bus Write Timing Waveform
Manager Bus Write Timing Waveform
Manager Bus Write Timing Waveform
by the state of the MD/C pin.
WRSL
STAT
LDCFG
SUP
INT
SEL
START
CBR
PARM
Command
1.
1
after the falling edge of MSTRB if MR/W is High.
2
Bit 7 of the status register under these conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible
higher priority operations that the IDT77V500 must support.
3
4
1
2
of the MD/C pin.
3
Bit 7 of the status register under these conditions indicates the command has been acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible
higher priority operations that the IDT77V500 must support.
4
IDT77V500
The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. That is, data is available to be read one asynchronous tAMD time
After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High
A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register).
Waveform illustrates first two bytes of data only. Additional bytes may be available based on command used.
Either a Read cycle was completed or a Status Acknowledge was executed immediately prior to the first MSTRB of this write waveform.
The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. The data placed on the MDATA pins is determined by the state
After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the IDT77V500 before proceeding. Reading a High
A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register).
Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is determined
Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is determined
Manager Command codes not defined in this table are not to be used.
M S TR B
MDATA
MR/W
MD/C
1
M S TR B
MDATA
MR/W
MD/C
Write Service Link Memory
Read IDT77V500 status
Load IDT77V400 Configuration Bits Passes configuration information to the IDT77V400.
Call setup
Initialize IDT77V500
Select a IDT77V500
End of IDT77V500 Initialization
Set up a CBR Scheduler
Set Parameters
8 ADDR bits
t
SMRW
t
Write first
ADDR
SMD
t
1
SM
IN
t
Command Name
t
HM
HMD
Write Data Byte 0
t
MCH
t
SMRW
t
t
t
SMD
DATA
HMRW
SM
T0
t
t
IN
t
HM
HMRW
HMD
t
MCYC
t
MCL
8 ADDR bits
ADDR
Write last
IN
Write Data Byte 12
DATA
T12
IN
t
MCH
Read Command
Write Cycle-
t
SMRW
t
CMD
t
MCYC
SM
Write into Service Link Memory to initialize scheduled service lists.
Reads the internal status of the IDT77V500. Available information includes various
error registers and counts.
Writes the appropriate information into an entry of the Per VC Memory to perform the
call setup function.
Initializes the internal configuration registers of the IDT77V500.
Selects the IDT77V500 to be enabled in a multiple device configuration.
Sets the IDT77V500 into an enabled state after it has been initialized.
Sets up a selected output service list in the Constant Bit Rate (CBR) mode.
Sets various parameters in the IDT77V500, including the CLP low water mark, the
EFCI low water mark, and the EPD low water mark.
t
MCL
IN
Write Command
t
SMRW
Write Cycle-
t
CMD
SM
Acknowledge Read
IN
1
t
AMD
Acknowledge Read
2
t
DATA
AMD
OUT
10 of 17
t
OHMD
DATA
Acknowledge Read
OUT
Command Description
2
t
OHMD
Acknowledge Read
DATA
OUT
Valid Command Acknowledge
DATA
Acknowledge Read –
OUT
Acknowledge Read
DATA
3
OUT
3
DATA
OUT
t
AMD
Valid Command Acknowledge
Read Byte 0
Acknowledge Read –
DATA
OUT
t
OHMD
DATA
OUT
4
Read Byte 1
DATA
3607 drw 09
03
07
08
09
0A
0B
0C
0D
0E
Code (in Hex)
OUT
April 11, 2001
4
3607 drw 08