KS8995MA Micrel Inc, KS8995MA Datasheet
KS8995MA
Specifications of KS8995MA
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KS8995MA Summary of contents
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... KS8995MA General Description The KS8995MA is a highly integrated Layer 2 managed switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set such as tag/port-based VLAN, quality of service (QoS) priority, management, MIB counters, dual MII interfaces and CPU control/data interfaces to effectively address both current and emerging Fast Ether- net applications ...
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... FTTx customer premise equipment • Managed Media converter Ordering Information Part Number Temp. Range KS8995MA 0°C to +70°C 128-Pin PQFP KSZ8995MA 0°C to +70°C 128-Pin PQFP KS8995MAI –40°C to +85°C 128-Pin PQFP 2 Micrel, Inc. Package Lead Finish Standard Lead-Free Standard May 2005 ...
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... KS8995MA Revision History Revision Date Summary of Changes 2.0 10/10/03 Created. 2.1 10/30/03 Editorial changes on electrical characteristics. 2.2 4/1/04 Editorial changes on the TTL input and output electrical characteristics. 2.3 1/19/05 Insert recommended reset circuit., Pg. 70. Editorial, Pg. 36 2.4 4/13/05 Changed VDDIO to 3.3V. ...
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... KS8995MA Table of Contents System Level Applications ......................................................................................................................................... 7 Pin Description by Number ........................................................................................................................................ 9 Pin Description by Name .......................................................................................................................................... 15 Pin Configuration ...................................................................................................................................................... 21 Introduction ........................................................................................................................................................... 22 Functional Overview: Physical Layer Transceiver ............................................................................................... 22 100BASE-TX Transmit ........................................................................................................................................ 22 100BASE-TX Receive ......................................................................................................................................... 22 PLL Clock Synthesizer ......................................................................................................................................... 22 Scrambler/De-scrambler (100BASE-TX only) ..................................................................................................... 22 100BASE-FX Operation ....................................................................................................................................... 22 100BASE-FX Signal Detection ............................................................................................................................ 22 100BASE-FX Far End Fault ................................................................................................................................ 23 10BASE-T Transmit ............................................................................................................................................. 23 10BASE-T Receive ...
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... KS8995MA Register Description ................................................................................................................................................. 39 Global Registers .................................................................................................................................................. 39 Register 0 (0x00): Chip ID0 ......................................................................................................................... 39 Register 1 (0x01): Chip ID1/Start Switch ..................................................................................................... 39 Register 2 (0x02): Global Control 0 ............................................................................................................. 40 Register 3 (0x03): Global Control 1 ............................................................................................................. 40 Register 4 (0x04): Global Control 2 ............................................................................................................. 41 Register 5 (0x05): Global Control 3 ............................................................................................................. 42 Register 6 (0x06): Global Control 4 ............................................................................................................. 42 Register 7 (0x07): Global Control 5 ............................................................................................................. 43 Register 8 (0x08): Global Control 6 ...
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... KS8995MA Register 112 (0x70): Indirect Data Register 8 ............................................................................................. 51 Register 113 (0x71): Indirect Data Register 7 ............................................................................................. 51 Register 114 (0x72): Indirect Data Register 6 ............................................................................................. 51 Register 115 (0x73): Indirect Data Register 5 ............................................................................................. 51 Register 116 (0x74): Indirect Data Register 4 ............................................................................................. 51 Register 117 (0x75): Indirect Data Register 3 ............................................................................................. 51 Register 118 (0x76): Indirect Data Register 2 ...
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... KS8995MA System Level Applications CPU WAN PHY & AFE (xDSL, CM...) May 2005 10/100 MAC 1 10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SPI/GPIO SPI Ethernet MAC MII-SW Ethernet MAC Figure 1. Broadband Gateway SPI/GPIO SPI MII-SW CPU Ethernet MAC Figure 2. Integrated Broadband Router ...
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... KS8995MA M9999-051305 10/100 10/100 PHY 1 MAC 1 10/100 10/100 MAC 2 PHY 2 10/100 10/100 PHY 3 MAC 3 10/100 10/100 MAC 4 PHY 4 10/100 10/100 MAC 5 PHY 5 Figure 3. Standalone Switch 8 Micrel, Inc. 5-port LAN May 2005 ...
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... KS8995MA Pin Description (by Number) Pin Number Pin Name Type 1 MDI-XDIS 2 GNDA Gnd 3 VDDAR 4 RXP1 5 RXM1 6 GNDA Gnd 7 TXP1 8 TXM1 9 VDDAT 10 RXP2 11 RXM2 12 GNDA Gnd 13 TXP2 14 TXM2 15 VDDAR 16 GNDA Gnd 17 ISET 18 VDDAT 19 RXP3 20 RXM3 21 GNDA Gnd 22 TXP3 23 TXM3 24 VDDAT 25 RXP4 26 RXM4 27 GNDA ...
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... KS8995MA Pin Number Pin Name Type 31 VDDAR 32 RXP5 33 RXM5 34 GNDA Gnd 35 TXP5 36 TXM5 37 VDDAT 38 FXSD5 39 FXSD4 40 GNDA Gnd 41 VDDAR 42 GNDA Gnd 43 VDDAR 44 GNDA Gnd 45 MUX1 46 MUX2 47 PWRDN_N 48 RESERVE 49 GNDD Gnd 50 VDDC 51 PMTXEN 52 PMTXD3 53 PMTXD2 54 PMTXD1 55 PMTXD0 56 PMTXER 57 PMTXC 58 GNDD Gnd 59 VDDIO ...
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... KS8995MA Pin Number Pin Name Type 61 PMRXDV Ipd/O 62 PMRXD3 Ipd/O 63 PMRXD2 Ipd/O 64 PMRXD1 Ipd/O 65 PMRXD0 Ipd/O 66 PMRXER Ipd/O 67 PCRS Ipd/O 68 PCOL Ipd/O 69 SMTXEN 70 SMTXD3 71 SMTXD2 72 SMTXD1 73 SMTXD0 74 SMTXER 75 SMTXC 76 GNDD Gnd 77 VDDIO 78 SMRXC 79 SMRXDV Ipd/O 80 SMRXD3 Ipd/O 81 SMRXD2 Ipd/O Note Power supply. ...
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... KS8995MA Pin Number Pin Name Type 82 SMRXD1 Ipd/O 83 SMRXD0 Ipd/O 84 SCOL Ipd/O 85 SCRS Ipd/O 86 SCONF1 87 SCONF0 88 GNDD 89 VDDC 90 LED5-2 Ipu/O 91 LED5-1 Ipu/O 92 LED5-0 Ipu/O 93 LED4-2 Ipu/O 94 LED4-1 Ipu/O 95 LED4-0 Ipu/O 96 LED3-2 Ipu/O 97 LED3-1 Ipu/O Note Power supply Input Output. I/O = Bidirectional. ...
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... SPI data transfer; 2 (2) not used in I Ipd Serial bus configuration pin. For this case, if the EEPROM is not present, the KS8995MA will start itself with the PS[1: default register values . Pin Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 ...
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... KS8995MA Pin Number Pin Name Type 119 SCANEN 120 NC 121 X1 122 X2 123 VDDAP 124 GNDA Gnd 125 VDDAR 126 GNDA Gnd 127 GNDA Gnd 128 TEST2 Note Power supply Input Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. ...
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... KS8995MA Pin Description (by Name) Pin Number Pin Name Type 39 FXSD4 38 FXSD5 124 GNDA Gnd 42 GNDA Gnd 44 GNDA Gnd 2 GNDA Gnd 16 GNDA Gnd 30 GNDA Gnd 6 GNDA Gnd 12 GNDA Gnd 21 GNDA Gnd 27 GNDA Gnd 34 GNDA Gnd 40 GNDA Gnd 120 NC 127 GNDA Gnd 126 ...
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... KS8995MA Pin Number Pin Name Type 97 LED3-1 Ipu/O 96 LED3-2 Ipu/O 95 LED4-0 Ipu/O 94 LED4-1 Ipu/O 93 LED4-2 Ipu/O 92 LED5-0 Ipu/O 91 LED5-1 Ipu/O 90 LED5-2 Ipu/O 107 MDC 108 MDIO 1 MDI-XDIS 45 MUX1 46 MUX2 68 PCOL Ipd/O 67 PCRS Ipd/O 60 PMRXC 65 PMRXD0 Ipd/O 64 PMRXD1 Ipd/O 63 PMRXD2 Ipd/O 62 PMRXD3 ...
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... PHY[5] MII transmit enable. Ipd 5 PHY[5] MII transmit error. Ipd Serial bus configuration pin. See “Pin 113.” Ipd Serial bus configuration pin. If EEPROM is not present, the KS8995MA will start itself with chip default (00)... Pin Configuration PS[1:0]=00 PS[1:0]=01 PS[1:0]=10 PS[1:0]=11 Ipu Full-chip power down ...
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... KS8995MA Pin Number Pin Name Type 86 SCONF1 85 SCRS Ipd/O 78 SMRXC 83 SMRXD0 Ipd/O 82 SMRXD1 Ipd/O 81 SMRXD2 Ipd/O 80 SMRXD3 Ipd/O 79 SMRXDV Ipd/O 75 SMTXC 73 SMTXD0 72 SMTXD1 71 SMTXD2 70 SMTXD3 69 SMTXEN 74 SMTXER Note Power supply Input Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. ...
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... See “Pin 113.” Ipu All Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N is high, the KS8995MA is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) Not used connect for normal operation. Factory test pin. ...
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... KS8995MA Pin Number Pin Name Type 89 VDDC 117 VDDC 59 VDDIO 77 VDDIO 100 VDDIO 121 X1 122 X2 Note Power supply Input Output. M9999-051305 (1) Port Pin Function P 1.8V digital core V P 1.8V digital core V P 3.3V digital V for digital I/O circuitry 3.3V digital V for digital I/O circuitry. ...
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... KS8995MA Pin Configuration 103 LED2-0 LED1-2 LED1-1 LED1-0 MDC MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N PS1 PS0 RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2 1 May 2005 128-Pin PQFP (PQ) 21 Micrel, Inc. 65 PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD ...
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... MII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed through the MII-P5 port. The KS8995MA has the flexibility to reside in a managed or unmanaged design managed design, a host processor has complete control of the KS8995MA via the SPI bus, or partial control via the MDC/MDIO interface. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time ...
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... Power Management The KS8995MA features a per port power down mode. To save power the user can power down ports that are not in use by setting port control registers or MII control registers. In addition, it also supports full chip power down mode. When activated, the entire chip will be shutdown. ...
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... The KS8995MA has a 64kB internal frame buffer. This resource is shared between all five ports. The buffer sharing mode can be programmed through Register 2. See “Register 2.” In one mode, ports are allowed to use any free buffers in the buffer pool. ...
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... KS8995MA May 2005 Start -Search VLAN table. NO VLAN ID PTF1=NULL -Ingress VLAN filtering VALID? -Discard NPVID check YES Search complete. FOUND Search based on Search Static Get PTF1 from DA or DA+FID Table static table. NOT FOUND Search complete. Dynamic FOUND This search is based on ...
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... IEEE standard 802.3x. Once the resource is freed up, the KS8995MA sends out the other flow control frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is also provided to prevent over-activation and deactivation of the flow control mechanism ...
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... Receive error MRXER Receive data bit 3 MRXD3 Receive data bit 2 MRXD2 Receive data bit 1 MRXD1 Receive data bit 0 MRXD0 Receive clock MRXC Table 2. MII – SW Signals 27 KS8995MA Signal PMTXEN PMTXER PMTXD[3] PMTXD[2] PMTXD[1] PMTXD[0] PMTXC PCOL PCRS PMRXDV PMRXER PMRXD[3] PMRXD[2] ...
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... MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation, if the device interfacing with the KS8995MA has an MRXER pin, it should be tied low. For MAC mode operation, if the device interfacing with the KS8995MA has an MTXER pin, it should be tied low. ...
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... KS8995MA will treat them as normal packets and an internal look-up will be performed. The KS8995MA uses a non-zero “port mask” to bypass the look-up result and override any port setting, regardless of port states (blocking, disable, listening, learning). Table 5 shows the egress rules when dealing with STPID. ...
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... KS8995MA Tx Port Ingress Tag Field “Tag Insertion” (0x810+ port mask) (0x810+ port mask) (0x810+ port mask) (0x810+ port mask) Not tagged Don’t care Table 5. STPID Egress Rules (Processor to Switch Port 5) For packets from regular ports (port 1 - port 4) to port 5, the port mask is used to tell the processor which port the packet was received on, defined as: “ ...
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... A packet, received on port 1, is destined to port 4 after the internal look-up. The KS8995MA will forward the packet to both port 4 and port 5. KS8995MA can optionally forward even “bad” received packets to port 5. ...
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... The rate limit starts from 0Kbps and goes up to the line rate in steps of 32Kbps. The KS8995MA uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. ...
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... KS8995MA Configuration Interface The KS8995MA can function as a managed switch or unmanaged switch EEPROM or micro-controller exists, the KS8995MA will operate from its default setting. Some default settings are configured via strap in options as indicated in the table below. Pin # Pin Name PU/PD 1 MDI-XDIS Ipd ...
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... LED indicator 1. Strap option: PU (default): enable PHY MII I/F. PD: tristate all PHY MII output. See “Pin 86 SCONF1.” Serial bus configuration pin. For this case, if the EEPROM is not present, the KS8995MA will start itself with the PS[1: default register values . Pin Configuration ...
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... SDA To configure the KS8995MA with a pre-configured EEPROM use the following steps the board level, connect pin 110 on the KS8995MA to the SCL pin on the EEPROM. Connect pin 111 on the KS8995MA to the SDA pin on the EEPROM. 2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00.” This puts the KS8995MA serial bus ...
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... Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure multiple read as shown in Figure 11. Note that read data is registered out of SPIQ on the falling edge of SPIC. 6. After configuration is written and verified, write a ‘1’ to Register 1 bit 0 to begin KS8995MA operation. M9999-051305 ...
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... KS8995MA SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ READ COMMAND May 2005 WRITE ADDRESS Figure 8. SPI Write Data Cycle READ ADDRESS Figure 9. SPI Read Data Cycle 37 Micrel, Inc WRITE DATA READ DATA M9999-051305 ...
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... The MIIM interface does not have access to all the configuration registers in the KS8995MA. It can only access the standard MII registers. See “MIIM Registers.” The SPI interface, on the other hand, can be used to access the entire KS8995MA feature set. ...
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... KS8995MA Register Description Offset Decimal Hex Description 0-1 0x00-0x01 Chip ID Registers 2-11 0x02-0x0B Global Control Registers 12-15 0x0C-0x0F Reserved 16-29 0x10-0x1D Port 1 Control Registers 30-31 0x1E-0x2F Port 1 Status Registers 32-45 0x20-0x2D Port 2 Control Registers 46-47 0x2E-0x2F Port 2 Status Registers 48-61 0x30-0x3D ...
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... KS8995MA Address Name Register 2 (0x02): Global Control 0 7 Reserved 6-4 802.1p Base Priority 3 Enable PHY MII 2 Buffer Share Mode 1 UNH Mode 0 Link Change Age Register 3 (0x03): Global Control 1 7 Pass All Frames 6 Reserved 5 IEEE 802.3x Transmit Flow Control Disable 4 IEEE 802.3x Receive ...
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... KS8995MA Address Name 2 Aging Enable 1 Fast age Enable 0 Aggressive Back Off Enable Register 4 (0x04): Global Control 2 7 Unicast Port-VLAN Mismatch Discard 6 Multicast Storm Protection Disable 5 Back Pressure Mode 4 Flow Control and Back Pressure Fair Mode 3 No Excessive Collision Drop 1, the switch will not drop packets when 16 or more ...
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... KS8995MA Address Name 1 Legal Maximum Packet Size Check Disable 0 Priority Buffer Reserve Register 5 (0x05): Global Control 3 7 802.1q VLAN Enable 6 IGMP Snoop Enable on Switch MII Interface 5 Enable Direct Mode on Switch MII Interface 4 Enable Pre-Tag on Switch MII Interface 3-2 Priority Scheme Select 1 Enable “ ...
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... KS8995MA Address Name 5 Switch MII Flow Control Enable 4 Switch MII 10BT 3 Null VID Replacement 2-0 Broadcast Storm Protection Rate Bit [10:8] Register 7 (0x07): Global Control 5 7-0 Broadcast Storm Protection Rate Bit [7:0] Note: 1. 148,800 frames/sec × 50ms/interval × frames/interval (approximately) = 0x4A. ...
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... KS8995MA Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 ...
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... KS8995MA Address Name 5 Transmit Sniff 4-0 Port VLAN Membership Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Port 4 Control 2 Register 82 (0x52): Port 5 Control 2 Address Name 7 Reserved 6 Ingress VLAN Filtering. 5 Discard Non-PVID Packets. 1, the switch will discard packets whose VID does not ...
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... KS8995MA Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Port 4 Control 3 Register 83 (0x53): Port 5 Control 3 Address Name 7-0 Default Tag [15:8] Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port 2 Control 4 Register 52 (0x34): Port 3 Control 4 Register 68 (0x44): Port 4 Control 4 ...
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... KS8995MA Register 24 (0x18): Port 1 Control 8 Register 40 (0x28): Port 2 Control 8 Register 56 (0x38): Port 3 Control 8 Register 72 (0x48): Port 4 Control 8 Register 88 (0x58): Port 5 Control 8 Address Name 7-0 Receive High Priority Rate Control [7:0] Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 ...
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... KS8995MA Address Name 3 High Priority Receive Rate Flow Control Enable 2 Transmit Differential Priority Rate Control 1 Low Priority Transmit Rate Control Enable 0 High Priority Transmit Rate Control Enable Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Port 3 Control 12 Register 76 (0x4C): Port 4 Control 12 ...
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... KS8995MA Address Name 0 Advertised 10BT Half-Duplex Capability Note: Port Control 12 and 13, and Port Status 0 contents can be accessed by MIIM (MDC/MDIO) interface via the standard MIIM register definition. Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Port 3 Control 13 Register 77 (0x4D): Port 4 Control 13 ...
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... KS8995MA Register 31 (0x1F): Port 1 Control 14 Register 47 (0x2F): Port 2 Control 14 Register 63 (0x3F): Port 3 Control 14 Register 79 (0x4F): Port 4 Control 14 Register 95 (0x5F): Port 5 Control 14 Address Name 7 PHY Loopback 6 Remote Loopback 5 PHY Isolate 4 Soft Reset 3 Force Link 2-1 Reserved 0 Far End Fault Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine priority from the 6 bit TOS field in the IP header ...
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... KS8995MA Address Name Register 106 (0x6A): MAC Address Register 2 7-0 MACA[31:24] Register 107 (0x6B): MAC Address Register 3 7-0 MACA[23:16] Register 108 (0x6C): MAC Address Register 4 7-0 MACA[15:8] Register 109 (0X6D): MAC Address Register 5 7-0 MACA[7:0] Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters. ...
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... KS8995MA Address Name Register 121 (0x79): Digital Testing Status 0 7-0 Factory Testing Register 122 (0x7A): Digital Testing Status 1 7-0 Factory Testing Register 123 (0x7B): Digital Testing Control 0 7-0 Factory Testing Register 124 (0x7C): Digital Testing Control 1 7-0 Factory Testing Register 125 (0x7D): Analog Testing Control 0 ...
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... The static table can only be accessed and controlled by an external SPI master (usually a processor). The entries in the static table will not be aged out by KS8995MA. An external device does all addition, modification and deletion. ...
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... KS8995MA Examples: (1) Static Address Table Read (read the 2nd entry) Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (60-56) Read Register 114 (55-48) Read Register 115 (47-40) ...
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... VID If 802.1q VLAN mode is enabled, KS8995MA assigns a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up. If the VID is not valid, the packet is dropped and no address learning occurs ...
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... KS8995MA Dynamic MAC Address This table is read only. The contents are maintained by the KS8995MA only. Address Name Format of Dynamic MAC Address Table (1K entries) 68 MAC Empty 67- Valid Entries 57-56 Time Stamp 55 Data Ready 54-52 Source Port 51-48 FID 47-0 MAC Address Examples: ...
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... KS8995MA MIB Counters The MIB counters are provided on per port basis. The indirect memory is as below: For port 1 Offset Counter Name 0x0 RxLoPriorityByte 0x1 RxHiPriorityByte 0x2 RxUndersizePkt 0x3 RxFragments 0x4 RxOversize 0x5 RxJabbers 0x6 RxSymbolError 0x7 RxCRCerror 0x8 RxAlignmentError 0x9 RxControl8808Pkts ...
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... KS8995MA For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f) For port 4, the base is 0x60, same offset definition (0x60-0x7f) For port 5, the base is 0x80, same offset definition (0x80-0x9f) Address Name Format of Per Port MIB Counters (16 entries) ...
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... KS8995MA (2) MIB counter read (read port counter) Write to Register 110 with 0x1c (read MIB counter selected) Write to Register 111 with 0x2e (trigger the read operation ) Then Read Register 117 (counter value 31-24 bit there was a counter overflow // If bit restart (reread) from this register ...
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... KS8995MA MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for port 1, “0x2” for port 2, “0x3” for port 3, “0x4” for port 4, and “ ...
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... KS8995MA Address Name Register 1: MII Status 15 T4 Capable 14 100 Full Capable 13 100 Half Capable 12 10 Full Capable 11 10 Half Capable 10-7 Reserved 6 Preamble Suppressed 5 AN Complete 4 Far End Fault 3 AN Capable 2 Link Status 1 Jabber Test 0 Extended Capable Register 2: PHYID HIGH 15-0 ...
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... KS8995MA Address Name Register 5: Link Partner Ability 15 Next Page 14 LP ACK 13 Remote Fault 12-11 Reserved 10 Pause 9 Reserved 8 Adv 100 Full 7 Adv 100 Half 6 Adv 10 Full 5 Adv 10 Half 4-0 Reserved M9999-051305 Description Not supported. Not supported. Not supported. Link partner pause capability. ...
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... KS8995MA Absolute Maximum Ratings Supply Voltage ( ............................. –0.5V to +2.4V DDAR, DDAP, DDC ( ........................................ –0.5V to +4.0V DDAT, DDIO Input Voltage ............................................... –0.5V to +4.0V Output Voltage ............................................ –0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ..................... 270°C Storage Temperature (T ) ....................... –55°C to +150°C S Electrical Characteristics Symbol Parameter 100BASE-TX Operation — All Ports 100% Utilization ...
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... KS8995MA Symbol Parameter 100BASE-TX Transmit (measured differentially after 1:1 transformer) Duty Cycle Distortion Overshoot V Reference Voltage of I SET SET Output Jitters 10BASE-TX Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer Peak Differential Output Voltage P Jitters Added Rise/Fall Times M9999-051305 ...
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... KS8995MA Timing Diagrams Receive Timing SCL SDA Figure 12. EEPROM Interface Input Receive Timing Diagram Transmit Timing SCL SDA Figure 13. EEPROM Interface Output Transmit Timing Diagram Symbol Parameter t Clock Cycle CYC1 t Set-Up Time S1 t Hold Time H1 t Output Valid OV1 May 2005 ...
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... KS8995MA Receive Timing MTXC MTXEN MTXD[0] Transmit Timing MRXC MRXDV MCOL MRXD[0] Symbol Parameter t Clock Cycle CYC2 t Set-Up Time S2 t Hold Time H2 t Output Valid O2 M9999-051305 ts2 tcyc2 th2 Figure 14. SNI Input Timing tcyc2 tov2 Figure 15. SNI Output Timing Table 18. SNI Timing Parameters 66 Micrel, Inc ...
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... KS8995MA Receive Timing MRXCLK MTXEN MTXER MTXD[3:0] Figure 16. MAC Mode MII Timing – Data Received from MII Transmit Timing MTXCLK MRXDV MRXD[3:0] Figure 17. MAC Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BASE-T) CYC3 t Clock Cycle (10BASE-T) ...
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... KS8995MA Receive Timing MTXCLK MTXEN MTXER MTXD[3:0] Figure 18. PHY Mode MII Timing – Data Received from MII Transmit Timing MRXCLK MRXDV MRXD[3:0] Figure 19. PHY Mode MII Timing – Data Transmitted from MII Symbol Parameter t Clock Cycle (100BASE-T) CYC4 t Clock Cycle (10BASE-T) ...
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... KS8995MA SPIS_N tCHSL SPIC tDVCH SPID SPIQ Symbol Parameter f Clock Frequency C t SPIS_N Inactive Hold Time CHSL t SPIS_N Active Set-Up Time SLCH t SPIS_N Active Hold Time CHSH t SPIS_N Inactive Set-Up Time SHCH t SPIS_N Deselect Time SHSL t Data Input Set-Up Time DVCH ...
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... KS8995MA SPIS_N SPIC tCLQX SPIQ SPID Symbol Parameter f Clock Frequency C t SPIQ Hold Time CLQX t Clock Low to SPIQ Valid CLQV t Clock High Time CH t Clock Low Time CL t SPIQ Rise Time QLQH t SPIQ Fall Time QHQL t SPIQ Disable Time SHQZ M9999-051305 ...
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... May 2005 tsr tcs tch trc Figure 22. Reset Timing Table 23. Reset Timing Parameters VCC R D1 10k KS8995MA RST D2 C 10µF D1, D2: 1N4148 Figure 23. Recommended Reset Circuit. VCC D1: 1N4148 D1 KS8995MA RST C 10µF 71 Min Typ CPU/FPGA RST_OUT_n R 10k Micrel, Inc. Max Units ...
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... KS8995MA Selection of Isolation Transformer One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max ...
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... KS8995MA Package Information MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. ...