KS8995MA Micrel Inc, KS8995MA Datasheet - Page 16

• Manufacturer Part Number: KS8995MA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995MA

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1017 - BOARD EVAL EXPERIMENT KS8995M
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant

KS8995MA
Note:
1. P = Power supply.
2. PU = Strap pin pull-up.
M9999-051305
Pin Number
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/ internal pull-up.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
NC = No connect.
PD = Strap pin pull-down.
107
108
97
96
95
94
93
92
91
90
45
46
68
67
60
65
64
63
62
61
66
1
Pin Name
MDI-XDIS
PMRXDV
PMRXER
PMRXD0
PMRXD1
PMRXD2
PMRXD3
PMRXC
LED3-1
LED3-2
LED4-0
LED4-1
LED4-2
LED5-0
LED5-1
LED5-2
MUX1
MUX2
PCOL
PCRS
MDIO
MDC
Type
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu
Ipd
NC
NC
I/O
O
(1)
Port
1-5
All
All
3
3
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
Pin Function
LED indicator 1.
LED indicator 2.
LED indicator 0.
LED indicator 1.
LED indicator 2.
LED indicator 0.
LED indicator 1. Strap option: PU (default) = enable PHY MII I/F
PD: tristate all PHY MII output. See “Pin 86 SCONF1.”
LED indicator 2. Strap option: aging setup. See “Aging” section.
(default) = aging enable; PD = aging disable.
Switch or PHY[5] MII management data clock.
Switch or PHY[5] MII management data I/O.
Disable auto MDI/MDI-X.
Factory test pins. MUX1 and MUX2 should be left unconnected for
normal operation.
Mode
Normal Operation
PHY[5] MII collision detect/force flow control. See “Register 18.”
For port 4 only. PD (default) = no force flow control. PU = force flow
control.
PHY[5] MII carrier sense/force duplex mode. See “Register 28.”
For port 4 only. PD (default) = force half-duplex if auto-negotiation is
disabled or fails. PU = force full-duplex if auto-negotiation is disabled
or fails.
PHY[5] MII receive clock. PHY mode MII.
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
PHY[5] MII receive data valid.
PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
16
(2)
MUX1
NC
Micrel, Inc.
May 2005
MUX2
NC