HCPL-4504-060E Avago Technologies US Inc., HCPL-4504-060E Datasheet - Page 13

• Manufacturer Part Number: HCPL-4504-060E
• Description: OPTOCOUPLER 1CH VDE GAASP 8-DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-4504-060E

• Input Type: DC
• Package / Case: 8-DIP (0.300", 7.62mm)
• Voltage - Isolation: 3750Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 8mA
• Propagation Delay High - Low @ If: 200ns @ 16mA
• Current - Dc Forward (if): 25mA
• Output Type: Open Collector
• Mounting Type: Through Hole
• Isolation Voltage: 3750 Vrms
• Maximum Forward Diode Current: 12 mA
• Output Device: Phototransistor
• Configuration: 1 Channel
• Current Transfer Ratio: 65 %
• Maximum Baud Rate: 1 MBps
• Maximum Forward Diode Voltage: 1.7 V
• Maximum Reverse Diode Voltage: 5 V
• Maximum Input Diode Current: 25 mA
• Maximum Power Dissipation: 100 mW
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Package Characteristics
Over recommended temperature (T
All typicals at T
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table (if applicable), your
equipment level safety specifi cation or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage. ”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
5. CURRENT TRANSFER RATIO in percent is defi ned as the ratio of output collector current, I
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The R
11. See Option 020 data sheet for more information.
12. Use of a 0.1 μF bypass capacitor connected between Pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (leakage detection
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (leakage detection
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second (leakage detection
16. This test is performed before the 100% Production test shown in the VDE 0884 Insulation Related Characteristics Table, if applicable.
17. The diff erence between t
13
Parameter
Input-Output
Momentary
Withstand
Voltage†
Input-Output
Resistance
Capacitance
(Input-Output)
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
the leading edge of the common mode pulse, V
transient immunity in a Logic Low level is the maximum tolerable (negative) dV
V
tolerable dV
V). Common mode transient immunity in a Logic Low level is the maximum tolerable dV
signal, V
current limit, I
current limit, I
current limit, I
Time and Propagation Delay Specifi cations section.)
CM
, to assure that the output will remain in a Logic Low state (i.e., V
L
= 20 kΩ, C
CM
, to assure that the output will remain in a Logic Low state (i.e., V
A
CM
= 25°C..
i-o
i-o
i-o
/dt on the leading edge of the common mode pulse, V
≤5 μA).
≤ 5 μA).
≤5 μA).
L
= 100 pF load represents an IPM (Intelligent Power Module) load.
Symbol
V
R
C
ISO
I-O
I-O
PLH
and t
Device
HCPL-4504
HCPL-0454
HCPL-J454
HCPL-4504
Option 020
HCNW4504
HCPL-4504
HCPL-0454
HCPL-J454
HCNW4504
HCPL-4504
HCPL-0454
HCPL-J454
HCNW4504
PHL
between any two devices (same part number) under the same test condition. (See Power Inverter Dead
A
= 0°C to 25°C) unless otherwise specifi ed.
CM
, to assure that the output will remain in a Logic High state (i.e., V
Min.
3750
3750
5000
5000
10
10
12
11
Typ.*
10
10
0.6
0.8
0.5
12
13
O
CM
< 0.8 V).
, to assure that the output will remain in a Logic High state (i.e., V
Max.
0.6
O
< 1.0 V).
CM
/dt on the trailing edge of the common mode pulse signal,
Units
V rms
Ω
pF
CM
O
, to the forward LED input current, I
/dt on the trailing edge of the common mode pulse
Test Conditions
RH ≤50%,
t = 1 min.,
T
V
T
T
f = 1 MHz
A
A
A
I-O
= 25°C
= 25°C
= 100°C
= 500 Vdc
O
> 2.0 V). Common mode
Figure
F
, times 100.
Note
6, 13,
16
6, 14,
16
15
6, 15,
16
6
6
6, 11,
CM
O
/dt on
> 3.0