CDB42428 Cirrus Logic Inc, CDB42428 Datasheet - Page 49

• Manufacturer Part Number: CDB42428
• Description: BOARD EVAL FOR CS42428 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42428

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42428/26/18/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1499

DS605F1
6.7.4
6.7.5
6.8
6.8.1
RATIO7(2
7
MASTER CLOCK SOURCE SELECT (SW_CTRLX)
FORCE PLL LOCK (FRC_PLL_LK)
OMCK/PLL_CLK Ratio (address 07h) (Read Only)
OMCK/PLL_CLK RATIO (RATIOX)
Default = 00
Function:
Default = 0
Function:
Default = xxxxxxxx
Function:
1
)
SW_CTRL1 SW_CTRL0
These two bits, along with the UNLOCK bit in register
on page
are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes
unlocked, RMCK will equal OMCK, but all internal and serial port timings are not valid.
When the FRC_PLL_LK bit is set to ‘1’b, the SW_CTRLX bits must be set to ‘00’b. If the PLL becomes
unlocked when the FRC_PLL_LK bit is set to ‘1’b, RMCK will not equal OMCK.
This bit is used to enable the PLL to lock to the ADC_LRCK with the absence of a clock signal on
OMCK. When set to a ‘1’b, the auto-detect sample frequency feature will be disabled and the
SW_CTRLX bits must be set to ‘00’b. The OMCK/PLL_CLK Ratio (address 07h) (Read Only) register
contents are not valid, and the PLL_CLK[2:0] bits will be set to ‘111’b. Use the DE-EMPH[1:0] bits to
properly apply de-emphasis filtering.
This register allows the user to find the exact absolute frequency of the recovered MCLK coming from
the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.
RATIO6(2
0
0
1
1
6
56, determine the master clock source for the CS42428. When SW_CTRL1 and SW_CTRL0
0
)
RATIO5(2
0
1
0
1
5
-1
Table 11. Master Clock Source Select
)
UNLOCK
RATIO4(2
X
X
0
1
0
1
4
Manual setting, MCLK sourced from PLL.
Manual setting, MCLK sourced from OMCK.
Hold, keep same MCLK source.Auto switch, MCLK
sourced from OMCK.
Auto switch, MCLK sourced from PLL.
Auto switch, MCLK sourced from OMCK.
-2
)
RATIO3(2
3
-3
“Interrupt Status (address 20h) (Read Only)”
)
Description
RATIO2(2
2
-4
)
RATIO1(2
1
-5
)
CS42428
RATIO0(2
0
-6
49
)