CDB42428 Cirrus Logic Inc, CDB42428 Datasheet - Page 50

• Manufacturer Part Number: CDB42428
• Description: BOARD EVAL FOR CS42428 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42428

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42428/26/18/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: Graphic User Interface
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1499

50
6.9
6.9.1
6.9.2
Reserved
7
Clock Status (address 08h) (Read Only)
SYSTEM CLOCK SELECTION (ACTIVE_CLK)
PLL CLOCK FREQUENCY (PLL_CLKX)
Note:
Default = x
0 - Output of PLL
1 - OMCK
Function:
Default = xxx
Function:
This bit identifies the source of the internal system clock (MCLK).
The CS42428 detects the ratio between the OMCK and the recovered clock from the PLL. Given the
absolute frequency of OMCK, this ratio may be used to determine the absolute frequency of the PLL
clock.
If a 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz clock is applied to OMCK and the OMCK_FREQX
bits are set accordingly (see
of the PLL clock is reflected in the PLL_CLKX bits according to
the PLL clock does not match one of the frequencies given in
est available value.
If the frequency of OMCK is not equal to 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz, the contents
of the PLL_CLKX bits will be inaccurate and should be disregarded. In this case, an external controller
may use the contents of the OMCK/PLL_CLK ratio register and the known OMCK frequency to de-
termine the absolute frequency of the PLL clock.
Reserved
These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.
6
PLL_CLK2
0
0
0
0
1
1
1
1
Reserved
5
Table 12. PLL Clock Frequency Detection
PLL_CLK1
“OMCK Frequency (OMCK Freqx)” on page
0
0
1
1
0
0
1
1
Reserved
4
PLL_CLK0
0
1
0
1
0
1
0
1
Active_CLK
3
Description
11.2896 MHz
16.3840 MHz
22.5792 MHz
24.5760 MHz
45.1584 MHz
49.1520 MHz
8.1920 MHz
12.288 MHz
PLL_CLK2
Table
Table
2
14, these bits will reflect the clos-
14. If the absolute frequency of
48), the absolute frequency
PLL_CLK1
1
CS42428
PLL_CLK0
DS605F1
0