CY3663 Cypress Semiconductor Corp, CY3663 Datasheet - Page 4

• Manufacturer Part Number: CY3663
• Description: KIT DEV EZ-OTG/EZ-HOST
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY3663

• Main Purpose: Interface, USB 2.0 Host/Controller
• Utilized Ic / Part: CY7C67300, CY7C67200
• Silicon Manufacturer: Cypress
• Application Sub Type: EZ-OTG / EZ-Host
• Kit Application Type: Interface
• Features: EZ HOST EZ OTG Development Tool
• Kit Contents: 2x Brds, CD, Doc, Cable, Pwr Sup
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Source Code
BAL.c
#include "cy7c67200_300.h"
typedef unsigned short uint16;
#define WRITE_REGISTER(address, value)
#define READ_REGISTER(address)
#define INPLACE_OR(address, value)
#define INPLACE_AND(address, value)
void writeCPLDADX(uint16 address)
{
}
void writeCPLDDATA(uint16 data)
{
}
int readCPLDDATA()
{
}
void writeCPLD(int address, int data)
{
}
int readCPLD(int address)
{
}
int main()
{
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0008);
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0020);
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0040);
INPLACE_OR(GPIO0_DIR_REG, 0x00FF);
WRITE_REGISTER(GPIO0_OUT_DATA_REG, address);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0040);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0020);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0008);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0008);
INPLACE_AND(GPIO1_OUT_DATA_REG,~0x0020);
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0040);
INPLACE_OR(GPIO0_DIR_REG, 0x00FF);
WRITE_REGISTER(GPIO0_OUT_DATA_REG, data);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0040);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0020);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0008);
uint16 data;
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0008);
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0020);
INPLACE_AND(GPIO1_OUT_DATA_REG, ~0x0080);
INPLACE_AND(GPIO0_DIR_REG, 0xFF00);
data = (READ_REGISTER(GPIO0_IN_DATA_REG) & 0x00FF);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0080);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x0020);
return data;
writeCPLDADX(address);
writeCPLDDATA(data);
writeCPLDADX(address);
return readCPLDDATA();
uint16 button_read = 0;
INPLACE_AND(UART_CTL_REG, 0xFE);
INPLACE_OR(GPIO0_OUT_DATA_REG, 0x00FF);
INPLACE_OR(GPIO1_OUT_DATA_REG, 0x00E8);
INPLACE_OR(GPIO0_DIR_REG, 0x00FF);
INPLACE_OR(GPIO1_DIR_REG, 0x00FF);
__asm( "or [%0], %1" : : "p" ((address)), "g" ((value)) )
__asm( "and [%0], %1" : : "p" ((address)), "g" ((value)) )
(*(volatile uint16 *) (address)) = ( (uint16) (value) )
(*(volatile uint16 *) (address))
/* A0 = 1 */
/* A0 = 0 */
/* nCS = 0 */
/* nWR = 0 */
/*Write Address*/
/* nWR = 1 */
/* nCS = 1 */
/* A0 = 1 */
/* A0 = 1 */
/* nCS = 0 */
/* nWR = 0 */
/*Write Address*/
/* nWR = 1 */
/* nCS = 1 */
/* A0 = 1 */
/* nCS = 0 */
/* nRD = 0 */
/*Write Address*/
/* nWR = 1 */
/* nCS = 1 */
/* Disable UART to free up GPIO 6 & 7 on EZ-OTG for CPLD*/
/* Data Port */
/* A0 = nCS = nRD = nWR = 1 */
Building an EZ-Host/OTG Project From Start to Finish
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