EVAL-AD7651CBZ Analog Devices Inc, EVAL-AD7651CBZ Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD7651CBZ
• Description: BOARD EVALUATION FOR AD7651
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7651CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 0 ~ 2.5 V
• Power (typ) @ Conditions: 16mW @ 100kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7651
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7651
SLAVE SERIAL INTERFACE
External Clock
The AD7651 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/ INT pin is held
HIGH. In this mode, several methods can be used to read the
data. The external serial clock is gated by CS . When CS and RD
are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. F
diagrams of these methods. Usually, because the AD7651 has a
longer acquisition phase than conversion phase, the data are
read immediately after conversion.
igure 34
and F
SDOUT
CNVST
SDOUT
BUSY
SCLK
BUSY
SCLK
SDIN
CS
igure 35
RD
t
16
Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
t
t
show the detailed timing
t
31
16
3
t
t
31
33
X
Figure 34. Slave Serial Data Timing for Reading (Read after Convert)
X
t
36
t
1
36
1
t
35
t
D15
35
t
37
D15
X15
t
37
t
34
2
2
EXT/INT = 1
D14
t
D14
X14
EXT/INT = 1
32
t
32
3
Rev. 0 | Page 22 of 28
3
D13
X13
D13
INVSCLK = 0
While the AD7651 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7651 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during the
latter half of BUSY HIGH.
INVSCLK = 0
14
14
15
15
D1
X1
D1
RD = 0
16
16
RD = 0
D0
X0
D0
17
X15
Y15
18
02964-0-017
02965-0-018
X14
Y14