CDB5534U Cirrus Logic Inc, CDB5534U Datasheet
CDB5534U
Specifications of CDB5534U
Related parts for CDB5534U
CDB5534U Summary of contents
Page 1
ADCs Features Chopper-stabilized PGIA (Programmable Gain Instrumentation Amplifier 64x) – 12 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x – 1200 pA Input Current with Gains >1 Delta-sigma Analog-to-digital Converter – Linearity Error: 0.0007% ...
Page 2
TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..........................................................4 ANALOG CHARACTERISTICS..........................................................................4 TYPICAL RMS NOISE (NV), CS5531/32/33/34 .................................................7 TYPICAL NOISE-FREE RESOLUTION(BITS), CS5532/34 ............................... DIGITAL CHARACTERISTICS .................................................................... DIGITAL CHARACTERISTICS ....................................................................8 DYNAMIC CHARACTERISTICS ........................................................................9 ABSOLUTE MAXIMUM RATINGS .....................................................................9 SWITCHING CHARACTERISTICS ...
Page 3
LIST OF FIGURES Figure 1. SDI Write Timing (Not to Scale)............................................................................... 11 Figure 2. SDO Read Timing (Not to Scale)............................................................................. 11 Figure 3. Multiplexer Configuration ......................................................................................... 12 Figure 4. Input models for AIN+ and AIN- pins ....................................................................... 13 Figure 5. ...
Page 4
CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (VA+, VD ±5%; VREF VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate Sps; Bipolar Mode; Gain = 32) (See Notes ...
Page 5
ANALOG CHARACTERISTICS (See Notes 1 and 2.) Parameter Analog Input Common Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode CVF Current on AIN+ or AIN- Input Current Noise Input Leakage for Mux when Off (at 25 °C) Off-channel Mux Isolation ...
Page 6
ANALOG CHARACTERISTICS (See Notes 1 and 2.) Power Supplies DC Power Supply Currents (Normal Mode) Power Consumption Normal Mode Standby Sleep Power Supply Rejection dc Positive Supplies dc Negative Supply 8. All outputs unloaded. All input CMOS levels. 9. Power ...
Page 7
TYPICAL RMS NOISE (nV), CS5531/32/33/34 (See notes 11, 12 and 13) Output Word -3 dB Filter Rate (Sps) Frequency (Hz) 7.5 1.94 15 3.88 30 7.75 60 15.5 120 31 240 62 480 122 960 230 1,920 390 3,840 780 ...
Page 8
V DIGITAL CHARACTERISTICS (VA+, VD ±5%; VA-, DGND = 0 V; See Notes 2 and 16.) Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage A0 and A1, I Low-level Output Voltage A0 and A1, ...
Page 9
DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Rate Filter Settling Time to 1/2 LSB (Full-scale Step Input) Single Conversion mode (Notes 17, 18, and 19) Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Sps 17. The ADCs ...
Page 10
SWITCHING CHARACTERISTICS (VA ±5%; VA- = -2.5V± VD+ = 3.0 V ±10 ±5%;DGND = 0 V; Levels: Logic Logic 1 = VD+; C Parameter ...
Page 11
DS289F5 Figure 1. SDI Write Timing ...
Page 12
GENERAL DESCRIPTION The CS5531/32/33/34 are highly integrated ∆Σ An- alog-to-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5531/33) and 24-bit (CS5532/34) performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process ...
Page 13
MHz). The common-mode plus signal range of the instru- mentation amplifier is (VA (VA+) - 1.7 V. Figure 4 illustrates the input models for the ...
Page 14
No Offset DAC An offset DAC was not included in the CS553X family because the high dynamic range of the con- verter eliminates the need for one. The offset regis- ter can be manipulated by the user to mimic ...
Page 15
Setups. Using the single conversion mode, an 8-bit com- mand word can be written into the serial port. ...
Page 16
RS=0) into the configuration register after performing a reset. The change in the reset sequence to include writing the RS bit back to 0 insures ...
Page 17
Command Register Quick Reference D7(MSB ARA CS1 BIT NAME VALUE FUNCTION D7 Command Bit Access Registers as 0 Arrays, ARA 1 D5-D4 Channel Select Bits, 00 CS1-CS0 Read/Write, R/W ...
Page 18
Command Register Descriptions READ/WRITE ALL OFFSET CALIBRATION REGISTERS D7(MSB Function: These commands are used to access the offset registers as arrays. R/W (Read/Write) 0 Write to selected registers. 1 Read from selected registers. READ/WRITE ALL GAIN ...
Page 19
READ/WRITE INDIVIDUAL GAIN REGISTER D7(MSB Function These commands are used to access each gain register separately. CS1 - CS0 decode the reg- isters accessed. R/W (Read/Write) 0 Write to selected register. 1 Read from selected register. ...
Page 20
PERFORM CONVERSION D7(MSB CSRP2 Function: These commands instruct the ADC to perform either a single, fully-settled conversion or con- tinuous conversions on the physical input channel pointed to by the pointer bits (CSRP2 - CRSP0) in the ...
Page 21
PERFORM CALIBRATION D7(MSB CSRP2 Function: These commands instruct the ADC to perform a calibration on the physical input channel se- lected by the setup register which is chosen by the command byte pointer bits (CSRP2 - CSRP0). ...
Page 22
Serial Port Interface The CS5531/32/33/34’s serial interface consists of four control lines: CS, SDI, SDO, SCLK. Figure 7 details the command and data word timing. CS, Chip Select, is the control line which enables access to the serial port. ...
Page 23
Reading/Writing On-Chip Registers The CS5531/32/33/34’s offset, gain, configuration, and channel-setup registers are readable and writ- able while the conversion data register is read only. As shown in Figure 7, to write to a particular regis- ter the user must ...
Page 24
The on-chip registers are initialized to the following default states: Configuration Register: 00000000(H) Offset Registers: 00000000(H) Gain Registers: 01000000(H) Channel Setup Registers: 00000000(H) After reset, the RS bit should be written back to logic 0 to complete ...
Page 25
Fine 1 φ Coarse 2 VREF C = 14pF ≤ MCLK VRS = ≤ V Figure 9. Input Reference Model when VRS = ...
Page 26
Configuration Register Descriptions D31(MSB) D30 D29 D28 D27 PSS PDW RS RV D15 D14 D13 D12 D11 PSS (Power Save Select)[31] 0 Standby Mode (Oscillator active, allows quick power-up). 1 Sleep Mode (Oscillator inactive). ...
Page 27
Filter Rate Select, FRS[19] 0 Use the default output word rates. 1 Scale all output word rates and their corresponding filter characteristics by a factor of 5/6. NU (Not Used)[18:0] 0 Must always be logic 0. Reserved for future upgrades. ...
Page 28
Channel-Setup Register Descriptions CSR #1 Setup 1 Bits <127:112> #4 Setup 7 Bits <31:16> D31(MSB) D30 D29 D28 D27 CS1 CS0 D15 D14 D13 D12 D11 CS1 CS0 CS1-CS0 (Channel Select Bits) [31:30] ...
Page 29
U/B (Unipolar / Bipolar) [22] [6] 0 Select Bipolar mode. 1 Select Unipolar mode. OL1-OL0 (Output Latch Bits) [21:20] [5:4] The latch bits will be set to the logic state of these bits upon command word execution when the output ...
Page 30
Calibration Calibration is used to set the zero and gain slope of the ADC’s transfer function. The CS5531/32/33/34 offer both self-calibration and system calibration. Note: After the ADCs are reset, they are functional and can perform measurements without being ...
Page 31
Performing Calibrations To perform a calibration, the user must send a com- mand byte with its MSB = 1, its pointer bits (CSRP2-CSRP0) set to address the desired Setup to calibrate, and the appropriate calibration bits (CC2- CC0) set ...
Page 32
System Calibration For the system calibration functions, the user must supply the converter’s calibration signals which rep- resent ground and full scale. When a system offset calibration is performed, a ground-referenced signal must be applied to the converters. Figure ...
Page 33
ADC, and may prematurely halt the calibration cycle. For maximum accuracy, calibrations should be per- formed for both offset and gain (selected by chang- ing the G2-G0 bits of the channel-setup registers). Note that only one gain ...
Page 34
The single conversion mode will take longer than conversions performed in the continuous conversion mode. The number of clock cycles a single conversion ...
Page 35
Table 2. Conversion Timing – Continuous Mode FRS (WR3-WR0) Clock Cycles (First Conversion) 0 0000 89528 ± 0001 171448 ± 0010 335288 ± 0011 662968 ± 0100 1318328 ± 1000 ...
Page 36
SDO falls to indicate that the calibration is complete. To perform additional calibrations, more commands must be issued. Note: The CSRs need not be written. If they are not initialized, all the Setups ...
Page 37
Table 4. Output Coding for 16-bit CS5531 and CS5533 Unipolar Input Offset Bipolar Input Voltage Binary Voltage >(VFS-1.5 LSB) FFFF >(VFS-1.5 LSB) VFS-1.5 LSB FFFF ------ VFS-1.5 LSB FFFE VFS/2-0.5 LSB 8000 ------ -0.5 LSB 7FFF +0.5 LSB 0001 ------ ...
Page 38
Digital Filter The CS5531/32/33/34 have linear phase digital fil- ters which are programmed to achieve a range of output word rates (OWRs) as stated in the Channel- Setup Register Descriptions section. The ADCs use 5 a Sinc digital filter ...
Page 39
Clock Generator The CS5531/32/33/34 include an on-chip inverting amplifier which can be connected with an external crystal to provide the master clock for the chip. Fig- ure 20 illustrates the on-chip oscillator. It includes loading capacitors and a feedback ...
Page 40
V Analog Supply - Figure 21. CS5532 Configured with a Single +5 V Supply 40 10 Ω 0.1 µ VA+ VD+ OSC2 18 VREF+ 17 VREF- 3 ...
Page 41
V Analog Supply - -2.5 V Analog Supply Figure 22. CS5532 Configured with ±2.5 V Analog Supplies +3 V Analog Supply - -3 V Analog Supply Figure 23. CS5532 Configured with ±3 V Analog Supplies DS289F5 0.1 µF 5 ...
Page 42
V Analog Supply 2. Analog Supply Figure 24. CS5532 Configured for Thermocouple Measurement V+ ( Ω 0.1 µF 5 VA+ VD+ 1 AIN1+ OSC2 2 AIN1 CS5532 ...
Page 43
Getting Started This A/D converter has several features. From a software programmer’s prospective, what should be done first? To begin, a 4.9152 MHz or 4.096 MHz crystal takes approximately start. To accommodate for this ...
Page 44
PIN DESCRIPTIONS DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT POSITIVE ANALOG POWER NEGATIVE ANALOG POWER LOGIC OUTPUT (ANALOG)/GUARD LOGIC OUTPUT (ANALOG) MASTER CLOCK MASTER CLOCK DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT ...
Page 45
SDI - Serial Data Input. SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SDO - Serial Data Output. SDO is the serial data output. It will output a ...
Page 46
SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the ADC transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is ...
Page 47
ORDERING INFORMATION Model Number Bits Channels Linearity Error (Max) Temperature Range CS5531- CS5531-ASZ 16 2 CS5533- CS5533-ASZ 16 4 CS5532- CS5532-ASZ 24 2 CS5534- CS5534-ASZ ENVIRONMENTAL, MANUFACTURING, & ...
Page 48
PACKAGE DRAWINGS 20 PIN SSOP PACKAGE DRAWING TOP VIEW DIM ∝ Notes: 1. “D” and “E1” are reference datums and do not included mold flash ...
Page 49
PIN SSOP PACKAGE DRAWING TOP VIEW DIM ∝ Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but ...
Page 50
Revisions REVISION DATE PP1 Jan 1999 Initial release PP6 Sep 2004 Added lead-free devices F1 Jul 2005 Updated with most-current characterization data. F2 Oct 2005 Updated Input Noise Current spec., Normal Mode Current spec., & note 9. F3 Nov 2006 ...