MAX107EVKIT Maxim Integrated Products, MAX107EVKIT Datasheet - Page 5

• Manufacturer Part Number: MAX107EVKIT
• Description: EVAL KIT FOR MAX107
• Manufacturer: Maxim Integrated Products

Specifications of MAX107EVKIT

• Number Of Adc's: 2
• Number Of Bits: 6
• Sampling Rate (per Second): 400M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 800 mVpp
• Power (typ) @ Conditions: 2.6W @ 400MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MAX105, MAX107
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(AV
= 0, f
otherwise noted. Typical values are at T
Note 1: INL and DNL is measured using a sine-histogram method.
Note 2: Input offset is the voltage required to cause a transition between codes 0 and -1.
Note 3: Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input voltage
Note 4: The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting algo
Note 5: Guaranteed by design and characterization.
Note 6: Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-mode
Note 7: Measured with analog power supplies tied to the same potential.
Note 8: Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.
Note 9: The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.
Note 10: Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.
Note 11: Harmonic distortion components two through five are included in the total harmonic distortion specification.
Note 12: Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input
Note 13: Measured with a differential probe, 1pF capacitance.
DREADY Duty Cycle
LVDS Output Rise-Time
LVDS Output Fall-Time
LVDS Differential Skew
DREADY Rise-Time
DREADY Fall-Time
Primary Port Pipeline Delay
Auxiliary Port Pipeline Delay
CC
CLK
= AV
level does not matter.
The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.
frequency of f
= 401.408MHz, C
PARAMETER
rithm (e.g. FFT).
voltage expressed in dB.
CC
I = AV
_______________________________________________________________________________________
CC
Dual, 6-Bit, 400Msps ADC with On-Chip,
IN
Q = AV
= 124.999 MHz.
L
= 1µF to AGND at REF, R
CC
R = +5V, OV
SYMBOL
t
t
RDREADY
FDREADY
t
t
t
RDATA
SKEW1
FDATA
t
t
A
PDP
PDA
= +25°C)
CC
I = OV
(Notes 5, 13)
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
Any differential pair
Any tw o LV D S outp ut si g nal s excep t D RE AD Y
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
CC
L
= 100Ω ±1% applied to digital LVDS outputs, T
Q = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
Wideband Input Amplifier
CONDITIONS
MIN
200
200
200
200
47
A
<100
TYP
<65
5
6
= T
MIN
MAX
to T
500
500
500
500
53
MAX
UNITS
Cycles
Cycles
, unless
Clock
Clock
ps
ps
ps
ps
ps
%
5