IRDC3841 International Rectifier, IRDC3841 Datasheet
IRDC3841
Specifications of IRDC3841
Related parts for IRDC3841
IRDC3841 Summary of contents
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SupIRBuck TM INTEGRATED 8A SYNCHRONOUS BUCK REGULATOR Features • Greater than 96% Maximum Efficiency • Wide Input Voltage Range 1.5V to 16V • Wide Output Voltage Range 0.7V to 0.9*Vin • Continuous 8A Load Capability • Integrated Bootstrap-diode • High ...
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ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND unless otherwise specified) • Vin ……………………………………………………. -0.3V to 25V • Vcc ……………….….…………….……..……….…… -0. (Note2) • Boot ……………………………………..……….…. -0.3V to 33V • SW …………………………………………..……… -0.3V to 25V(DC), -4V to 25V(AC, 100ns) • ...
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Block Diagram Fig. 2. Simplified block diagram of the IR3841 06/18/09 IR3841MPbF 3 ...
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Pin Description Pin Name Sequence pin. Use two external resistors to set Simultaneous Power up 1 Seq sequencing. If this pin is not used connect to Vcc. Inverting input to the error amplifier. This pin is connected directly to the ...
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Recommended Operating Conditions Symbol Definition V Input Voltage in V Supply Voltage cc Boot to SW Supply Voltage V Output Voltage o I Output Current o Fs Switching Frequency T Junction Temperature j Electrical Specifications Unless otherwise specified, these specification ...
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Electrical Specifications (continued) Unless otherwise specified, these specification apply over 4.5V< V Typical values are specified Parameter Symbol Oscillator Rt Voltage Frequency F S Accuracy Ramp Amplitude Vramp Ramp Offset Ramp (os) Min Pulse Width ...
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Electrical Specifications (continued) Unless otherwise specified, these specification apply over 4.5V< V Typical values are specified Parameter SYM Thermal Shutdown Thermal Shutdown Note4 Hysteresis Note4 Power Good Power Good upper VPG+ Fb Rising Threshold Delay ...
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TYPICAL OPERATING CHARACTERISTICS (-40 Icc(Stan db y) 240.0 220.0 200.0 180.0 -40 - 701.0 700.5 700.0 699.5 699.0 698.5 698.0 697.5 697.0 696.5 696.0 -40 -20 0 ...
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Typical Efficiency and Power Loss Curves Vin=12V, Vcc=5V, Io=1A-8A, Room Temperature, No Air Flow The table below shows the inductors used for each of the output voltages in the efficiency measurement. Vout (V) Vout ( 1.2 1.2 1.5 ...
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Typical Efficiency and Power Loss Curves Vin=5V, Vcc=5V, Io=1A-8A, Fs=600kHz, Room Temperature, No Air Flow For all the output voltages, L=0.51uH (DCR=0.29 mΩ, P/N: 59PR9876N 1.0 1.5 2.0 2.5 3.0 0.7Vout 1.2Vout ...
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Circuit Description THEORY OF OPERATION Introduction The IR3841 uses a PWM voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The switching frequency is programmable from 250kHz ...
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Figure 3c. shows the recommended startup sequence for sequenced operation of IR3841 with Enable used as logic input. Fig. 3c. Recommended startup sequence, Sequenced operation Pre-Bias Startup IR3841 is able to start up into pre-charged output, which prevents oscillation disturbances ...
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Operating Frequency The switching frequency can be programmed between 250kHz – 1500kHz by connecting an external resistor from R pin to Gnd. Table 1 t tabulates the oscillator frequency versus R Table 1. Switching Frequency and I External Resistor (R ...
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Thermal Shutdown Temperature sensing is provided inside IR3841. The trip threshold is typically set to 140 trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature ...
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TIMING DIAGRAM OF PGOOD FUNCTION Fig.9a IR3841 Non-Sequenced Operation (Seq=Vcc) Fig.9b IR3841 Sequencing Operation 06/18/09 IR3841MPbF 15 ...
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Minimum on time Considerations The minimum ON time is the shortest amount of time for which the Control FET may be reliably turned on, and this depends on the internal timing delays. For the IR3841, the typical minimum on-time is ...
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Application Information Design Example: The following example is a typical application for IR3841. The application circuit is shown on page 23 13.2V max 1 ≤ ...
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Vc across C6 remains approximately unchanged and the voltage at the Boot pin becomes ≅ + − .......... .......... .......... Boot Boot IR3841 PGnd Fig. ...
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Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance ...
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V Z OUT E REF Gain(dB) H( Fig. 14. Type II compensation network and its asymptotic gain plot The transfer function ( given by: e ...
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V OUT E REF Gain(dB) H( Fig.15. Type III Compensation network and its asymptotic gain plot The ...
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Detailed calculation of compensation TypeIII o Θ = Desired Phase Margin 70 − Θ sin 17.63 kHz Θ sin 1 + Θ sin 567.1 kHz P ...
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... Panasonic- ECG 0603, 50V, X7R, 10% Panasonic - ECG Thick Film, 0603,1/10W,1% Rohm Thick Film, 0603,1/10W,1% Rohm Thick Film, 0603,1/10W,1% Panasonic - ECG 0603, 50V, X7R, 10% Panasonic - ECG SupIRBuck PQFN 5x6mm International Rectifier IR3841MPbF Vo C7 2.2nF R10 130 Co=6X22uF R9 2.55 K Part Number EEV-FK1E331P ECJ-3YX1C106K ...
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-8A, Room Temperature, No Air Flow Fig. 17. Start Load :Enable Fig. 19. Start ...
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TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=0-8A, Room Temperature, No Air Flow Fig. 23. Transient Response step 06/18/09 IR3841MPbF out 4 out 25 ...
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TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=8A, Room Temperature, No Air Flow Fig. 24. Bode Plot at 8A load shows a bandwidth of 111kHz and phase margin of 50 degrees 06/18/09 IR3841MPbF 26 ...
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... PCB. To such as effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. Figure 25 illustrates the feedback implementation of the layout guidelines outlined above, on the IRDC3841 4 layer demoboard. PGnd Vin Vin PGnd Vout Vout IR3841MPbF ...
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... Single point connection between AGND & PGND, should be close to the SupIRBuck, kept away from noise sources. Fig.25c. IRDC3841 demoboard layout considerations – Mid Layer 1 Fig.25d. IRDC3841 demoboard layout considerations – Mid Layer 2 06/18/09 IR3841MPbF PGnd Power Vin Ground Plane AGnd ...
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PCB Metal and Components Placement Lead lands (the 11 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to ...
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Solder Resist It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should ...
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Stencil Design • The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited ...
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IR WORLD HEADQUARTERS: This product has been designed and qualified for the Consumer market 06/18/09 BOTTOM VIEW 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Visit us at www.irf.com for sales contact information Data and specifications subject ...