EVAL-AD5444EBZ Analog Devices Inc, EVAL-AD5444EBZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD5444EBZ
• Description: BOARD EVALUATION FOR AD5444
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5444EBZ

• Number Of Dac's: 1
• Number Of Bits: 12
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 2.7M
• Data Interface: Serial
• Settling Time: 16ns
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 125°C
• Utilized Ic / Part: AD5444
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5444/AD5446 DAC is
through a serial bus that uses standard protocol compatible
with microcontrollers and DSP processors. The communica-
tions channel is a 3-wire interface consisting of a clock signal, a
data signal, and a synchronization signal. The AD5444/AD5446
requires a 16-bit word, with the default being data valid on the
falling edge of SCLK, but this can be changed using the control
bits in the data-word.
ADSP-21xx to AD5444/AD5446 Interface
The ADSP-21xx family of DSPs is easily interfaced to the
AD5444/AD5446 DAC without the need for extra glue logic.
Figure 46 is an example of an SPI interface between the DAC
and the ADSP-2191M. SCK of the DSP drives the serial clock
line, SCLK. SYNC is driven from one of the port lines, in this
case SPIxSEL .
A serial interface between the DAC and DSP SPORT is shown
in Figure 47. In this interface example, SPORT0 is used to trans-
fer data to the DAC shift register. Transmission is initiated by
writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSP serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.
Communication between two devices at a given clock speed
is possible when the following specifications are compatible:
frame sync delay and frame sync setup-and-hold, data delay
and data setup-and-hold, and SCLK width. The DAC inter-
face expects a t
time) of 13 ns minimum. See the ADSP-21xx User Manual for
information on clock and frame sync frequencies for the
SPORT register.
Table 11 shows the setup for the SPORT control register.
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-2191*
ADSP-2101/
ADSP-2103/
ADSP-2191*
Figure 46. ADSP-2191M SPI to AD5444/AD5446 Interface
Figure 47. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to
SPIxSEL
SCLK
MOSI
SCK
TFS
4
DT
( SYNC falling edge to SCLK falling edge setup
AD5444/AD5446 Interface
SYNC
SDIN
SCLK
AD5444/AD5446*
SYNC
SDIN
SCLK
AD5446*
AD5444/
Rev. C | Page 21 of 28
Table 11. SPORT Control Register Setup
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
ADSP-BF5xx to AD5444/AD5446 Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the ADSP-BF5xx
and the AD5444/AD5446 DAC is shown in Figure 48. In this
configuration, data is transferred through the MOSI (master
output/slave input) pin. SYNC is driven by the SPI chip select
pin, which is a reconfigured programmable flag pin.
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 49. When the SPORT is
enabled, initiate transmission by writing a word to the Tx register.
The data is clocked out on each rising edge of the DSPs serial
clock and clocked into the DAC input shift register on the
falling edge of its SCLK. The DAC output is updated by using
the transmit frame synchronization (TFS) line to provide a
SYNC signal.
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
ADSP-BF5xx*
ADSP-BF5xx*
Figure 48. ADSP-BF5xx to AD5444/AD5446 Interface
Figure 49. ADSP-BF5xx to AD5444/AD5446 Interface
SPIxSEL
SCLK
MOSI
Setting
1
1
00
1
1
1
1111
SCK
TFS
DT
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
AD5444/AD5446
AD5444/AD5446*
AD5444/AD5446*
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK